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Explorer
Explorer
551 Views
Registered: ‎08-15-2014

Warnings about IDELAYE3

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hi,I met below warnings in my simulation,

May I know how to clean this since eI must use DELAY_FORMA=TIME? Is it because I am using the wrong libs?
Warning: [Unisim IDELAYE3-1] Ultrascale IDELAYCTRL and I/ODELAYE3, RST simulation behaviour may not match hardware behaviour when DELAY_FORMAT = TIME, if SelectIO User Guide recommendation for I/ODELAY connections or reset sequence are not followed. For more information, refer to the Select IO Userguide Instance: tb_hstdm.u_NV_hstdm_top.u_NV_hstdm_sourcesyn_bank_receive.u_NV_hstdm_bank_receive.pinmux_rx_bus[9].lvds_pinmux_rx.io[20].i_dnlvds_pinmux_rx_iserdes.i_idelay
^CInterrupt at time 269226780

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Xilinx Employee
Xilinx Employee
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Registered: ‎07-16-2008

回复: Warnings about IDELAYE3

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This check is embedded in the IDELAYE3 unisim model. It is triggered under the following condition.

always @(RST_in) begin
if (RST_in === 1'b1 && DELAY_FORMAT_REG == "TIME")
$display("Warning: [Unisim %s-1] Ultrascale IDELAYCTRL and I/ODELAYE3, RST simulation behaviour may not match hardware behaviour when DELAY_FORMAT = TIME, if SelectIO User Guide recommendation for I/ODELAY connections or reset sequence are not followed. For more information, refer to the Select IO Userguide Instance: %m", MODULE_NAME);
end

This is to inform the user of the importance of reset sequence. Otherwise you may get not get expected hardware behavior.

Please take a look at UG571, pg193, section "Component Mode Reset Sequence".

http://www.xilinx.com/support/documentation/user_guides/ug571-ultrascale-selectio.pdf

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Xilinx Employee
Xilinx Employee
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Registered: ‎07-16-2008

回复: Warnings about IDELAYE3

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This check is embedded in the IDELAYE3 unisim model. It is triggered under the following condition.

always @(RST_in) begin
if (RST_in === 1'b1 && DELAY_FORMAT_REG == "TIME")
$display("Warning: [Unisim %s-1] Ultrascale IDELAYCTRL and I/ODELAYE3, RST simulation behaviour may not match hardware behaviour when DELAY_FORMAT = TIME, if SelectIO User Guide recommendation for I/ODELAY connections or reset sequence are not followed. For more information, refer to the Select IO Userguide Instance: %m", MODULE_NAME);
end

This is to inform the user of the importance of reset sequence. Otherwise you may get not get expected hardware behavior.

Please take a look at UG571, pg193, section "Component Mode Reset Sequence".

http://www.xilinx.com/support/documentation/user_guides/ug571-ultrascale-selectio.pdf

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