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Registered: ‎06-07-2012

What causes message: Virtual Object tree message too large



I run my simulation and I get the following message:

Virtual Object tree message too large: 32194953


Obviously I am abusing the capacities of Vivado 2018.3.  I searched for that message on the Xilinx web site and I can't find any hit.  Anybody knows what is abused?  Is it related to the wave config window or the Locals window or is it fundamental in the simulation?




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3 Replies
Registered: ‎05-31-2017

Re: What causes message: Virtual Object tree message too large

Hi @jlarin,

When are you facing this while running simulation, I mean does this message occur when you are doing something specific in simulation? Or does it occur with every design you simulate? Also, can you please share a snippet of the message??

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Registered: ‎09-15-2016

Re: What causes message: Virtual Object tree message too large

Hi @jlarin,

Can you please share the screenshot of the error message and the log file.

What steps have you followed and at which step does this issue occur? Does this happen with all the designs or is this issue specific to one design?

For me it looks like a out of memory issue. Can you please check if it occurs when logging the wave? Do you have large number of signals added into the Waveform GUI? If yes, please try reducing them and check.

How much memory does your machine have? Can you please check the resource utilization while running xsim?


Thanks & Regards,
Sravanthi B
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Registered: ‎06-07-2012

Re: What causes message: Virtual Object tree message too large


Hi @shameera, Hi @bandi,

I traced the code while I was looking at memory utilisation. I confirm this is a memory utilisation issue and it is not related to waveform display (I closed the display and I encountered the condition on the memory allocation).  The snippet is shown above.


My machine (Windows7-64) has 12 GB of memory and it gets all used as when the message appears. Here is a very simplified version of the file containing the problematic code:

`timescale 1ns / 1ps
package ImagePkg;

class Image;

    shortint image[];
    int pgm_size_x, pgm_size_y, pgm_max;

    task load_image;

        integer fileId;
        int i;
        int pixel;

        string chaine;
        fileId = $fopen( "whatever.pgm", "r" );

        i=$fscanf(fileId,"%d %d", pgm_size_x, pgm_size_y);    

        image = new[pgm_size_x * pgm_size_y];
        for (int j = 0; j < (pgm_size_x * pgm_size_y); j += 1) begin
            i=$fscanf(fileId," %d", pixel);
            image[j] = pixel;

    endtask : load_image

endclass :  Image    

endpackage : ImagePkg

The object uses a dynamic array to hold 16-bit data. The array is allocated at runtime at 1984x1200 which should allocate a dynamic array of 1984x1200x2 bytes = 4 761 600 bytes.


When the allocation takes place at the line "image = new[pgm_size_x * pgm_size_y];" the memory footprint of the xsimk.exe process increased by about 2 GB.  I understand that vhdl std_logic type have 9 states and signals consume more memory in the simulator than the actual memory they represent.  However I chose to use SystemVerilog 2-state type (shortint) and dynamic array especially because it should be the most efficient way of allocating large array. A factor of 450 between what I want to allocate and the memory actually consumed seems quite excessive.

Is there any preferred type and allocation method for an array for testbench purposes in Vivado simulator? I mean, this isn't a signal that will be put in waveform and there will never be X or Z in that array, so there must be an efficient way to allocating that array.


Thank you for your support,



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