UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
Visitor bluquette
Visitor
98 Views
Registered: ‎08-14-2019

Wrapping SystemVerilog in VHDL: Size Mismatch for Array Ports

I am trying to wrap a SystemVerilog module in VHDL. The SystemVerilog module has ports which are 3-dimensional arrays. I created VHDL array types to match the SystemVerilog. 

When trying to elaborate this design for simulation, I see the following error in elaborate.log:

ERROR: [VRFC 10-3714] size mismatch in mixed language port association, verilog port 'in_3d_arr' 
ERROR: [VRFC 10-3714] size mismatch in mixed language port association, verilog port 'out_3d_arr'

Also, I noticed the code synthesizes without producing this error or similar warning.

I have attached a project which represents a trivial case which produces the error. Is this type of port connection supported? More detail below.

Brandon

 

The SystemVerilog being wrapped is:

 

module sv_top(
	       in_3d_arr,
	      out_3d_arr);

   input wire  [31:0] in_3d_arr [0:3] [0:7];
   output wire [31:0] out_3d_arr [0:3] [0:7];

   assign out_3d_arr = in_3d_arr;
endmodule

 

The VHDL doing the wrapping is:

 

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
use work.types_support_package.all;
  
entity vhdl_top is

port (
  in_3d_arr : in three_d_arr;
  out_3d_arr : out three_d_arr
);

end vhdl_top;

architecture rtl of vhdl_top is

  component sv_top
   port (
     in_3d_arr : in three_d_arr;
     out_3d_arr : out three_d_arr
   );
  end component;

begin

  sv_top_inst: sv_top
    port map(
      in_3d_arr  => in_3d_arr,
      out_3d_arr => out_3d_arr);

end;

 

The VHDL type definition is:

 

library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all;

package types_support_package is
  
  type two_d_arr is array(0 to 7) of std_logic_vector(31 downto 0);
  type three_d_arr is array (0 to 3) of two_d_arr;
  
end types_support_package;
0 Kudos
1 Reply
Scholar richardhead
Scholar
89 Views
Registered: ‎08-01-2012

Re: Wrapping SystemVerilog in VHDL: Size Mismatch for Array Ports

A couple of symantics here, which are probably why its not working.

The SV array is a 3d array type but 2 dimensions are unpacked and 1d is packed

Your VHDL array is not a 3d array. It is a 1D array of a 1D array of a 1D array.

Hence why I think the compiler is getting confused.

When crossing the code boundary, its usually safer to stick to a max of 1D (you might be able to to 1D of 1D into a 1d packed/unpacked).

Anything more complicated is likely not to work.

0 Kudos