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Adventurer
Adventurer
8,353 Views
Registered: ‎06-05-2012

Writing testbench

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Hello, everyone,

 

I am a new designer on FPGA design. I am doing a video processing project. The camera captures the imag and sends the data to DDR3, then the FPGA chip fetches the data from DDR3 to process the image.

 

I am just wandering how can I arrange the testbench for the whole project? Can someone give me some idea?

 

In my idea, I can simulate the HDMI timing based on HDMI spec, and the frame data saved in the external file. while the problem is that the system clock in this project is 200MHz, and the HDMI clock(75MHz) comes from 200MHz by PLL.while, in the tb file, the clock for reading the data from the image data is 75MHz, so I don't know how can I give this clock ? In sum, I don't understand how can i give a internal signal of the uut in the tb file, if this internal signal is the stimulus. the frame size is 720p.

 

Please give me some idea. By the way could some one give me some complicate tb examples, since there are few on the websit. thanks!

 

 

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1 Solution

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Advisor eilert
Advisor
10,672 Views
Registered: ‎08-14-2007

Re: Writing testbench

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Hi,

in a testbench you can do most anything.

Especially stuff that wouldn't work in synthesis.

 

If the HDMI clock is an output from the FPGA, you can use that signal in your testbench to trigger some process that reads a pixel value from a file and then applies this to some FPGA input. No problem.

 

For the FPGAs PLLs and DCMs there are models in the XilinxCorelib.

 

The bigggest problem in the end might be the DDR memory.

Even if you find some behavioral HDL models that you can instantiate in your testbench, these models are very complex and simulating read/write of some large image (720p) may take days(!).

We faced such a problem some time ago and we already used some big multi CPU server with lots of RAM.

 

Have a nice simulation

  Eilert

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12 Replies
Advisor eilert
Advisor
10,673 Views
Registered: ‎08-14-2007

Re: Writing testbench

Jump to solution

Hi,

in a testbench you can do most anything.

Especially stuff that wouldn't work in synthesis.

 

If the HDMI clock is an output from the FPGA, you can use that signal in your testbench to trigger some process that reads a pixel value from a file and then applies this to some FPGA input. No problem.

 

For the FPGAs PLLs and DCMs there are models in the XilinxCorelib.

 

The bigggest problem in the end might be the DDR memory.

Even if you find some behavioral HDL models that you can instantiate in your testbench, these models are very complex and simulating read/write of some large image (720p) may take days(!).

We faced such a problem some time ago and we already used some big multi CPU server with lots of RAM.

 

Have a nice simulation

  Eilert

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Adventurer
Adventurer
8,338 Views
Registered: ‎06-05-2012

Re: Writing testbench

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Thank you Eilert.
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Adventurer
Adventurer
8,333 Views
Registered: ‎06-05-2012

Re: Writing testbench

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Hi, eilrt,

As you memtioned, I clock signal generated from FPGA as is used in testbench, but I still cannot fetch the pixel data from external file. the follows is the code, could you help me pick up the mistakes ? thank you  very much.

 

 

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    21:30:20 09/11/2012 
// Design Name: 
// Module Name:    tb_FPGA_TOP 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module tb_FPGA_TOP();
	
	reg				PSW_RST		        ; // (i)  push switch, reset
	reg				CLK_200M_P	        ; // (i)  clock 200MHz, positive
	reg				CLK_200M_N	        ; // (i)  clock 200MHz, negative
	reg	  [23:0]	HDMIR0_D			; // (i)  input Data	
	
	// HDMI0 Rx Video IF
	// reg			HDMIR0_CLK		    ;
	// reg			HDMIR0_VS		    ;
	// reg			HDMIR0_HS		    ;
	// reg			HDMIR0_DE		    ;

	// reg   [29:0]	HDMIR0_D		    ;


	// HDMI0 Tx Video IF
	//wire			HDMIT0_CLK		    ;
	wire			HDMIT0_VS		    ;
	wire			HDMIT0_HS		    ;
	wire			HDMIT0_DE		    ;

	//wire  [23:0]	HDMIT0_D		    ;

    // MCB1 DDR3-SDRAM Interface
	wire			MCB1_DDR3_CK	    ; // (o)  mcb1 DDR3-SDRAM Clock, positive
	wire			MCB1_DDR3_XCK	    ; // (o)  mcb1 DDR3-SDRAM Clock, negative
	wire			MCB1_DDR3_CKE	    ; // (o)  mcb1 DDR3-SDRAM Clock enable
	wire			MCB1_DDR3_RASN	    ; // (o)  mcb1 DDR3-SDRAM Row address enable, low active
	wire			MCB1_DDR3_CASN	    ; // (o)  mcb1 DDR3-SDRAM Column address enable, low active
	wire			MCB1_DDR3_WEN	    ; // (o)  mcb1 DDR3-SDRAM Write enable, low active
	wire	[12:0]	MCB1_DDR3_A	        ; // (o)  mcb1 DDR3-SDRAM Memory address
	wire	[ 2:0]	MCB1_DDR3_BA	    ; // (o)  mcb1 DDR3-SDRAM Bank address
	wire			MCB1_DDR3_ODT	    ; // (o)  mcb1 DDR3-SDRAM on die termination
	wire	[15:0]	MCB1_DDR3_DQ	    ; // (io) mcb1 DDR3-SDRAM Data bus
	wire	[ 1:0]	MCB1_DDR3_DM	    ; // (o)  mcb1 DDR3-SDRAM Data Mask
	wire	[ 1:0]	MCB1_DDR3_DQS	    ; // (io) mcb1 DDR3-SDRAM Data Strobe, positive
	wire	[ 1:0]	MCB1_DDR3_XDQS	    ; // (io) mcb1 DDR3-SDRAM Data Strobe, negative
	wire			MCB1_DDR3_RESETN    ; // (o)  mcb1 DDR3-SDRAM reset

    wire           MCB1_RZQ            ;
    wire           MCB1_ZIO            ;

    // MCB5 DDR3-SDRAM Interface
	wire			MCB5_DDR3_CK	    ; // (o)  mcb5 DDR3-SDRAM Clock, positive
	wire			MCB5_DDR3_XCK	    ; // (o)  mcb5 DDR3-SDRAM Clock, negative
	wire			MCB5_DDR3_CKE	    ; // (o)  mcb5 DDR3-SDRAM Clock enable
	wire			MCB5_DDR3_RASN	    ; // (o)  mcb5 DDR3-SDRAM Row address enable, low active
	wire			MCB5_DDR3_CASN	    ; // (o)  mcb5 DDR3-SDRAM Column address enable, low active
	wire			MCB5_DDR3_WEN	    ; // (o)  mcb5 DDR3-SDRAM Write enable, low active
	wire	[12:0]	MCB5_DDR3_A	        ; // (o)  mcb5 DDR3-SDRAM Memory address
	wire	[ 2:0]	MCB5_DDR3_BA	    ; // (o)  mcb5 DDR3-SDRAM Bank address
	wire			MCB5_DDR3_ODT	    ; // (o)  mcb5 DDR3-SDRAM on die termination
	wire	[15:0]	MCB5_DDR3_DQ	    ; // (io) mcb5 DDR3-SDRAM Data bus
	wire	[ 1:0]	MCB5_DDR3_DM	    ; // (o)  mcb5 DDR3-SDRAM Data Mask
	wire	[ 1:0]	MCB5_DDR3_DQS	    ; // (io) mcb5 DDR3-SDRAM Data Strobe, positive
	wire	[ 1:0]	MCB5_DDR3_XDQS	    ; // (io) mcb5 DDR3-SDRAM Data Strobe, negative
	wire			MCB5_DDR3_RESETN    ; // (o)  mcb5 DDR3-SDRAM reset

    wire           MCB5_RZQ            ;
    wire           MCB5_ZIO            ;

	// DSW&PSHSW&LED
	// input	[ 9:0]	DSW				    ; // (i)  DSW[15:0]
	wire	[ 7:0]	LED				    ; // (o)  LED[15:0]
	wire	[ 7:0]	PH				    ; // (o)  PH[15:0]
	
	//HDMI timing	
	wire	o_s_span_hdmit_vs	   ;
	wire	o_s_span_hdmit_hs	   ;
	wire	o_s_span_hdmit_de	       ;
	wire	span_clk_75			   ;
	
	
	
	
	reg	[23:0]	frame_memory [921600*5-1:0]	;			// five frame: frame size 1280x720. RGB one 24-pixel
	
	integer i	; 
	//reg j;
	
	
	always 
		#5 CLK_200M_P = ~CLK_200M_P	;
		
	always	
		#5 CLK_200M_N = ~CLK_200M_N	;
		
	initial
	begin
		CLK_200M_P = 1'b1;
		CLK_200M_N = 1'b0;
		PSW_RST = 1'b0	;
		i = 0;
		//j = 0;
		
		$readmemb("frame5.txt",frame_memory);
		
		#15	PSW_RST = 1'b1;
		#20 PSW_RST = 1'b0;
	end
	
	always @ (posedge span_clk_75)  // i suspect this part have some problem 
		begin 
			if(o_s_span_hdmit_de == 1)
			begin
				HDMIR0_D = frame_memory[i] ;
				i = i + 1;
			if(i>921600*5)
				begin
					$finish;
				end
			end
		end
	
	initial 
	#500000000 $finish;
	
	
	FPGA_TOP uut_FPGA_TOP (
    .PSW_RST(PSW_RST), 
    .CLK_200M_P(CLK_200M_P), 
    .CLK_200M_N(CLK_200M_N), 
	.HDMIR0_D(HDMIR0_D),
	
    .HDMIT0_VS(HDMIT0_VS), 
    .HDMIT0_HS(HDMIT0_HS), 
    .HDMIT0_DE(HDMIT0_DE), 
    //.HDMIT0_D(HDMIT0_D), 
	
    .MCB1_DDR3_CK(MCB1_DDR3_CK), 
    .MCB1_DDR3_XCK(MCB1_DDR3_XCK), 
    .MCB1_DDR3_CKE(MCB1_DDR3_CKE), 
    .MCB1_DDR3_RASN(MCB1_DDR3_RASN), 
    .MCB1_DDR3_CASN(MCB1_DDR3_CASN), 
    .MCB1_DDR3_WEN(MCB1_DDR3_WEN), 
    .MCB1_DDR3_A(MCB1_DDR3_A), 
    .MCB1_DDR3_BA(MCB1_DDR3_BA), 
    .MCB1_DDR3_ODT(MCB1_DDR3_ODT), 
    .MCB1_DDR3_DQ(MCB1_DDR3_DQ), 
    .MCB1_DDR3_DM(MCB1_DDR3_DM), 
    .MCB1_DDR3_DQS(MCB1_DDR3_DQS), 
    .MCB1_DDR3_XDQS(MCB1_DDR3_XDQS), 
    .MCB1_DDR3_RESETN(MCB1_DDR3_RESETN), 
    .MCB1_RZQ(MCB1_RZQ), 
    .MCB1_ZIO(MCB1_ZIO), 
	
    .MCB5_DDR3_CK(MCB5_DDR3_CK), 
    .MCB5_DDR3_XCK(MCB5_DDR3_XCK), 
    .MCB5_DDR3_CKE(MCB5_DDR3_CKE), 
    .MCB5_DDR3_RASN(MCB5_DDR3_RASN), 
    .MCB5_DDR3_CASN(MCB5_DDR3_CASN), 
    .MCB5_DDR3_WEN(MCB5_DDR3_WEN), 
    .MCB5_DDR3_A(MCB5_DDR3_A), 
    .MCB5_DDR3_BA(MCB5_DDR3_BA), 
    .MCB5_DDR3_ODT(MCB5_DDR3_ODT), 
    .MCB5_DDR3_DQ(MCB5_DDR3_DQ), 
    .MCB5_DDR3_DM(MCB5_DDR3_DM), 
    .MCB5_DDR3_DQS(MCB5_DDR3_DQS), 
    .MCB5_DDR3_XDQS(MCB5_DDR3_XDQS), 
    .MCB5_DDR3_RESETN(MCB5_DDR3_RESETN), 
    .MCB5_RZQ(MCB5_RZQ), 
    .MCB5_ZIO(MCB5_ZIO), 
	
    .o_s_span_hdmit_vs(o_s_span_hdmit_vs),
    .o_s_span_hdmit_hs(o_s_span_hdmit_hs),
    .o_s_span_hdmit_de(o_s_span_hdmit_de),
    .span_clk_75(span_clk_75),
	
    .PH(PH), 
    .LED(LED)
    );

	
	
endmodule

 


if(o_s_span_hdmit_de == 1)
begin
HDMIR0_D = frame_memory[i] ;
i = i + 1;
if(i>921600*5)
begin
$finish;
end
end
end

initial
#500000000 $finish;


FPGA_TOP uut_FPGA_TOP (
.PSW_RST(PSW_RST),
.CLK_200M_P(CLK_200M_P),
.CLK_200M_N(CLK_200M_N),
.HDMIR0_D(HDMIR0_D),

.HDMIT0_VS(HDMIT0_VS),
.HDMIT0_HS(HDMIT0_HS),
.HDMIT0_DE(HDMIT0_DE),
//.HDMIT0_D(HDMIT0_D),

.MCB1_DDR3_CK(MCB1_DDR3_CK),
.MCB1_DDR3_XCK(MCB1_DDR3_XCK),
.MCB1_DDR3_CKE(MCB1_DDR3_CKE),
.MCB1_DDR3_RASN(MCB1_DDR3_RASN),
.MCB1_DDR3_CASN(MCB1_DDR3_CASN),
.MCB1_DDR3_WEN(MCB1_DDR3_WEN),
.MCB1_DDR3_A(MCB1_DDR3_A),
.MCB1_DDR3_BA(MCB1_DDR3_BA),
.MCB1_DDR3_ODT(MCB1_DDR3_ODT),
.MCB1_DDR3_DQ(MCB1_DDR3_DQ),
.MCB1_DDR3_DM(MCB1_DDR3_DM),
.MCB1_DDR3_DQS(MCB1_DDR3_DQS),
.MCB1_DDR3_XDQS(MCB1_DDR3_XDQS),
.MCB1_DDR3_RESETN(MCB1_DDR3_RESETN),
.MCB1_RZQ(MCB1_RZQ),
.MCB1_ZIO(MCB1_ZIO),

.MCB5_DDR3_CK(MCB5_DDR3_CK),
.MCB5_DDR3_XCK(MCB5_DDR3_XCK),
.MCB5_DDR3_CKE(MCB5_DDR3_CKE),
.MCB5_DDR3_RASN(MCB5_DDR3_RASN),
.MCB5_DDR3_CASN(MCB5_DDR3_CASN),
.MCB5_DDR3_WEN(MCB5_DDR3_WEN),
.MCB5_DDR3_A(MCB5_DDR3_A),
.MCB5_DDR3_BA(MCB5_DDR3_BA),
.MCB5_DDR3_ODT(MCB5_DDR3_ODT),
.MCB5_DDR3_DQ(MCB5_DDR3_DQ),
.MCB5_DDR3_DM(MCB5_DDR3_DM),
.MCB5_DDR3_DQS(MCB5_DDR3_DQS),
.MCB5_DDR3_XDQS(MCB5_DDR3_XDQS),
.MCB5_DDR3_RESETN(MCB5_DDR3_RESETN),
.MCB5_RZQ(MCB5_RZQ),
.MCB5_ZIO(MCB5_ZIO),

.o_s_span_hdmit_vs(o_s_span_hdmit_vs),
.o_s_span_hdmit_hs(o_s_span_hdmit_hs),
.o_s_span_hdmit_de(o_s_span_hdmit_de),
.span_clk_75(span_clk_75),

.PH(PH),
.LED(LED)
);



endmodule

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Advisor eilert
Advisor
8,325 Views
Registered: ‎08-14-2007

Re: Writing testbench

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Hi,

what error message do you get?

 

It might be that the verilog compiler is kind of picky because of the whitespace behind the @.

Try

   always @(posedge span_clk_75)

 

If that's not it, check the Input file and how it will be read in by the simulator.

If you are using Modelsim, you can stop the simulation after reading in the file and then inspect the contents of the target array. I'm not sure how to do this in ISIM, but the values from the file should sequentially appear in the HDMIR0_D signal.

 

There are many more signals that could be checked. What can be seen in the Waveform and how exactly looks the data in the text file? Sometimes even simple things like trailing whitespaces or empty lines can cause funny results.

 

Have a nice simulation

  Eilert

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Adventurer
Adventurer
8,316 Views
Registered: ‎06-05-2012

Re: Writing testbench

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Hello, Eilert,

 

Thank you for your reply. I have modied some interal signal from uut as the input signal for testbench. while, I still can't fetch the data from the external file. the follows is the corrected code and the wave result.pls.help me to check the code, especially, the read memory part. thank you very much.

 

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    21:30:20 09/11/2012 
// Design Name: 
// Module Name:    tb_FPGA_TOP 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module tb_FPGA_TOP();
	
	reg				PSW_RST		        ; // (i)  push switch, reset
	reg				CLK_200M_P	        ; // (i)  clock 200MHz, positive
	reg				CLK_200M_N	        ; // (i)  clock 200MHz, negative
	reg	  [23:0]	HDMIR0_D			; // (i)  input Data	
	
	// HDMI0 Tx Video IF
	//wire			HDMIT0_CLK		    ;
	wire			HDMIT0_VS		    ;
	wire			HDMIT0_HS		    ;
	wire			HDMIT0_DE		    ;

	//wire  [23:0]	HDMIT0_D		    ;

    // MCB1 DDR3-SDRAM Interface
	wire			MCB1_DDR3_CK	    ; // (o)  mcb1 DDR3-SDRAM Clock, positive
	wire			MCB1_DDR3_XCK	    ; // (o)  mcb1 DDR3-SDRAM Clock, negative
	wire			MCB1_DDR3_CKE	    ; // (o)  mcb1 DDR3-SDRAM Clock enable
	wire			MCB1_DDR3_RASN	    ; // (o)  mcb1 DDR3-SDRAM Row address enable, low active
	wire			MCB1_DDR3_CASN	    ; // (o)  mcb1 DDR3-SDRAM Column address enable, low active
	wire			MCB1_DDR3_WEN	    ; // (o)  mcb1 DDR3-SDRAM Write enable, low active
	wire	[12:0]	MCB1_DDR3_A	        ; // (o)  mcb1 DDR3-SDRAM Memory address
	wire	[ 2:0]	MCB1_DDR3_BA	    ; // (o)  mcb1 DDR3-SDRAM Bank address
	wire			MCB1_DDR3_ODT	    ; // (o)  mcb1 DDR3-SDRAM on die termination
	wire	[15:0]	MCB1_DDR3_DQ	    ; // (io) mcb1 DDR3-SDRAM Data bus
	wire	[ 1:0]	MCB1_DDR3_DM	    ; // (o)  mcb1 DDR3-SDRAM Data Mask
	wire	[ 1:0]	MCB1_DDR3_DQS	    ; // (io) mcb1 DDR3-SDRAM Data Strobe, positive
	wire	[ 1:0]	MCB1_DDR3_XDQS	    ; // (io) mcb1 DDR3-SDRAM Data Strobe, negative
	wire			MCB1_DDR3_RESETN    ; // (o)  mcb1 DDR3-SDRAM reset

    wire           MCB1_RZQ            ;
    wire           MCB1_ZIO            ;

    // MCB5 DDR3-SDRAM Interface
	wire			MCB5_DDR3_CK	    ; // (o)  mcb5 DDR3-SDRAM Clock, positive
	wire			MCB5_DDR3_XCK	    ; // (o)  mcb5 DDR3-SDRAM Clock, negative
	wire			MCB5_DDR3_CKE	    ; // (o)  mcb5 DDR3-SDRAM Clock enable
	wire			MCB5_DDR3_RASN	    ; // (o)  mcb5 DDR3-SDRAM Row address enable, low active
	wire			MCB5_DDR3_CASN	    ; // (o)  mcb5 DDR3-SDRAM Column address enable, low active
	wire			MCB5_DDR3_WEN	    ; // (o)  mcb5 DDR3-SDRAM Write enable, low active
	wire	[12:0]	MCB5_DDR3_A	        ; // (o)  mcb5 DDR3-SDRAM Memory address
	wire	[ 2:0]	MCB5_DDR3_BA	    ; // (o)  mcb5 DDR3-SDRAM Bank address
	wire			MCB5_DDR3_ODT	    ; // (o)  mcb5 DDR3-SDRAM on die termination
	wire	[15:0]	MCB5_DDR3_DQ	    ; // (io) mcb5 DDR3-SDRAM Data bus
	wire	[ 1:0]	MCB5_DDR3_DM	    ; // (o)  mcb5 DDR3-SDRAM Data Mask
	wire	[ 1:0]	MCB5_DDR3_DQS	    ; // (io) mcb5 DDR3-SDRAM Data Strobe, positive
	wire	[ 1:0]	MCB5_DDR3_XDQS	    ; // (io) mcb5 DDR3-SDRAM Data Strobe, negative
	wire			MCB5_DDR3_RESETN    ; // (o)  mcb5 DDR3-SDRAM reset

    wire           MCB5_RZQ            ;
    wire           MCB5_ZIO            ;

	// DSW&PSHSW&LED
	// input	[ 9:0]	DSW				    ; // (i)  DSW[15:0]
	wire	[ 7:0]	LED				    ; // (o)  LED[15:0]
	wire	[ 7:0]	PH				    ; // (o)  PH[15:0]
	
	
	wire 		o_span_clk_75 = tb_FPGA_TOP.uut_FPGA_TOP.span_clk_75;
	wire 		o_s_span_hdmit_de = tb_FPGA_TOP.uut_FPGA_TOP.s_span_hdmit_de	;
	
	
	
	reg	[23:0]	frame_memory[921600*5-1:0]	;			// five frame: frame size 1280x720. RGB one 24-pixel
	
	integer i	; 
	
	always 
		#5 CLK_200M_P = ~CLK_200M_P	;
		
	always	
		#5 CLK_200M_N = ~CLK_200M_N	;
		
	initial
	begin
		CLK_200M_P = 1'b1;
		CLK_200M_N = 1'b0;
		PSW_RST = 1'b0	;
		i = 0;
		//j = 0;
		
		$readmemb("J:\ProjectWorkSpace\MotionEstimation\example_1_1010\example_1\M1\PROJECT\frame5.txt",frame_memory);
		
		#15	PSW_RST = 1'b1;
		#20 PSW_RST = 1'b0;
	end
	
	always @ (posedge o_span_clk_75)
		begin 
			if(o_s_span_hdmit_de == 1)
			begin
				HDMIR0_D = frame_memory[i];
				i = i + 1;
				if(i>921600*5)
				begin
					$finish;
				end
			end
		end
	
	initial 
	#500000000 $finish;
	
	
	FPGA_TOP uut_FPGA_TOP (
    .PSW_RST(PSW_RST), 
    .CLK_200M_P(CLK_200M_P), 
    .CLK_200M_N(CLK_200M_N), 
	.HDMIR0_D(HDMIR0_D),
	
    .HDMIT0_VS(HDMIT0_VS), 
    .HDMIT0_HS(HDMIT0_HS), 
    .HDMIT0_DE(HDMIT0_DE), 
    //.HDMIT0_D(HDMIT0_D), 
	
    .MCB1_DDR3_CK(MCB1_DDR3_CK), 
    .MCB1_DDR3_XCK(MCB1_DDR3_XCK), 
    .MCB1_DDR3_CKE(MCB1_DDR3_CKE), 
    .MCB1_DDR3_RASN(MCB1_DDR3_RASN), 
    .MCB1_DDR3_CASN(MCB1_DDR3_CASN), 
    .MCB1_DDR3_WEN(MCB1_DDR3_WEN), 
    .MCB1_DDR3_A(MCB1_DDR3_A), 
    .MCB1_DDR3_BA(MCB1_DDR3_BA), 
    .MCB1_DDR3_ODT(MCB1_DDR3_ODT), 
    .MCB1_DDR3_DQ(MCB1_DDR3_DQ), 
    .MCB1_DDR3_DM(MCB1_DDR3_DM), 
    .MCB1_DDR3_DQS(MCB1_DDR3_DQS), 
    .MCB1_DDR3_XDQS(MCB1_DDR3_XDQS), 
    .MCB1_DDR3_RESETN(MCB1_DDR3_RESETN), 
    .MCB1_RZQ(MCB1_RZQ), 
    .MCB1_ZIO(MCB1_ZIO), 
	
    .MCB5_DDR3_CK(MCB5_DDR3_CK), 
    .MCB5_DDR3_XCK(MCB5_DDR3_XCK), 
    .MCB5_DDR3_CKE(MCB5_DDR3_CKE), 
    .MCB5_DDR3_RASN(MCB5_DDR3_RASN), 
    .MCB5_DDR3_CASN(MCB5_DDR3_CASN), 
    .MCB5_DDR3_WEN(MCB5_DDR3_WEN), 
    .MCB5_DDR3_A(MCB5_DDR3_A), 
    .MCB5_DDR3_BA(MCB5_DDR3_BA), 
    .MCB5_DDR3_ODT(MCB5_DDR3_ODT), 
    .MCB5_DDR3_DQ(MCB5_DDR3_DQ), 
    .MCB5_DDR3_DM(MCB5_DDR3_DM), 
    .MCB5_DDR3_DQS(MCB5_DDR3_DQS), 
    .MCB5_DDR3_XDQS(MCB5_DDR3_XDQS), 
    .MCB5_DDR3_RESETN(MCB5_DDR3_RESETN), 
    .MCB5_RZQ(MCB5_RZQ), 
    .MCB5_ZIO(MCB5_ZIO), 
	
    .PH(PH), 
    .LED(LED)
    );	
endmodule

20120914220116.jpg


 

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Advisor eilert
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8,283 Views
Registered: ‎08-14-2007

Re: Writing testbench

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Hi,

just take a look at the waveform.

The 75MHz clock is not toggling (yet), therefore nothing can be seen on the data signal.

 

DCMs/PLLs need some time to stabilize their outputs. DCMs have a locked signal to indicate this.

The behavior of the Clock output might not be specified before that.

 

Also, while I found this assignment:

	wire 		o_span_clk_75 = tb_FPGA_TOP.uut_FPGA_TOP.span_clk_75;

I did not find this output on the UUTs port list.

Are you accessing some internal signal here?

Make sure you do this correctly. Are there any warnings or infos coming from Modelsim?

 

Make sure that your instantiated DUT is working correctly and all library elements are bound correctly.

 

Some other question:

While you have instantiated your design, I 'm missing the model instantiations for the DDR3 memory.

 

Also, now that it's clear that you are using modelsim, have you taken a look at the frame_memory contents?

That signal is accessible in your object window, and there you can inspect all the values to ensure that the file read operation nworked correctly.

 

 

Have a nice simulation

  Eilert

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Adventurer
Adventurer
8,266 Views
Registered: ‎06-05-2012

Re: Writing testbench

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Hi, eliert

 

Thank you for your reply. It seems that I can find the mistake, I cannot get the system clock 200M. this clock is from the different 200M input clock from outside. I have tried my best to debug this signal, but I failed.

 

The attached document is the project file, including uut and tb. please help me to check this signal. Really appreciate your kindily help. 

 

the clock signal is in the CLK_RST file.

 

 

 

 

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Adventurer
Adventurer
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Registered: ‎06-05-2012

Re: Writing testbench

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Hi eliert,

Thank you for your reply. The attachments is the source as your request.
I meet the trap in the DDR interface, from the simulation result, I learned that the ddr cannot work. it is always stay the IDLE status. tracing back the control signal for ddr, i think the problems is s_calib_done(in u_memc1_wrapper file). referring the mig core example, the signal should be high after completion of all phases of calibration. but this signal in my project is alway low.

 

Could you help me to pick up this mistakes? please. thank you very  mcuh.

 

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Adventurer
Adventurer
8,252 Views
Registered: ‎06-05-2012

Re: Writing testbench

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Hi eiliert,

 

the interesting thing is I can detect calib_done works well in chipscope. why it cannot work well in simulation?

 

Regards

 

chipscope image.jpg

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Advisor eilert
Advisor
4,419 Views
Registered: ‎08-14-2007

Re: Writing testbench

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Hi,

your Testbench as shown in one of your recent posts does not have an instance of the DDR devices.

So, the DDR-Controllers of the FPGA_TOP design will get no feedback and therefore stay in some idle/init phase.

 

Since some of your sources carry the copyright of Tokyo Elektron Device Ltd. (In other words: Inrevium) check the provided sources that came with your board. There should be some subdirectory with the DDR device models that are compatible to the ones used on your evaluation board. These need to be instantiated properly in your testbench, so you can do a board simulation (FPGA + DDR devices).

 

Have a nice simulation

  Eilert 

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Highlighted
Newbie smanohar
Newbie
4,300 Views
Registered: ‎02-01-2013

Re: Writing testbench

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Respected Sir,

 

I'm Also doing the same video processing Project Only sir, my Algorithm is Face detection algorithm using Haar Classifier .

I Want to Know How to store the pixel data to RAM? and how to Rerive that pixel data?. in before that i dont know how to conver the video in TXT file... Plz help ..

 

Thank you ver much

 

By, Mano.H

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Observer bhaskar872
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4,161 Views
Registered: ‎06-23-2012

Re: Writing testbench

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respected sir,I am getting the testbench data into input after 1 clock cycle ???how can  I eliminate the delay and what is the cause of the delay??

 

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