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Teacher
Teacher
14,191 Views
Registered: ‎07-09-2009

XADC simulation file locatoin

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Using the XADC block from xilinx

 

have this warnign in xilinx simulation

 

Warning: *** Warning: The analog data file for XADC was not found. Use the SIM_MONITOR_FILE generic to specify the input analog data file name

 

As all the files are under source control , the 'root' of the files could vary, 

    even the drive leter, I use D, others use E, joys of 'experts' and windows.

 

so can only put in a relative path for the file.

 

but where is xilxin simulation looking fo rthe file, so I can put a relative path from that ..

 

 

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Teacher
Teacher
22,857 Views
Registered: ‎07-09-2009

I think I have the solution and reason now sorted for this.

 

The text file needs to go in the same folder as the IP. 

 

BUT :

 

this does not work if you use the new Xilinx containers for IP .....

 

These IP containers are basicaly a ZIP file  of the IP folder, with a none .zip extention to stop windows / linux et all seeing into the folder....  

 

I have not managed to make the adc simulation file work with IP containers, and have gone back to normal folders.

    Now the xadc simulation file works just fine....

 

My thoughts, with this and the crazy size of the containers, I'm dumping containers.

 

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Moderator
Moderator
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Registered: ‎07-31-2012

Hi,

 

Please tell which version of software tool and xadc IP version you are using.

Could you share you desing file with testbench if it is not IP example project?

 

Regards

Praveen


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Teacher
Teacher
13,293 Views
Registered: ‎07-09-2009

vivado 2015.4

 

built in simulator of vivado,

 

all files built in vivado 2015.4

 

IP stored out of context, in the 'new' xilinx zipped IP folder structure.

 

I can make a demo project for you,

   with the xadc in , if that helps you..

 

send us an email address in a pm if you want that

 

 

 

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Teacher
Teacher
22,858 Views
Registered: ‎07-09-2009

I think I have the solution and reason now sorted for this.

 

The text file needs to go in the same folder as the IP. 

 

BUT :

 

this does not work if you use the new Xilinx containers for IP .....

 

These IP containers are basicaly a ZIP file  of the IP folder, with a none .zip extention to stop windows / linux et all seeing into the folder....  

 

I have not managed to make the adc simulation file work with IP containers, and have gone back to normal folders.

    Now the xadc simulation file works just fine....

 

My thoughts, with this and the crazy size of the containers, I'm dumping containers.

 

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Observer
Observer
12,232 Views
Registered: ‎09-30-2015
You mean you found a way to simulate the .txt file? Can you help me too?
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Xilinx Employee
Xilinx Employee
11,597 Views
Registered: ‎09-05-2007

Having just struggled to make simulation work myself I thought I would record what I found out and needed to do to achieve success.

 

I was using a VHDL design flow in Vivado but I suspect that the potential issues are common to all flows.

 

Firstly, the text file containing the analogue stimulus can be located anywhere you like providing you specify the path and its name in the ‘SIM_MONITOR_FILE’ generic. It doesn’t seem to matter if you use forward or reverse slashes when defining the path. For example…

 

SIM_MONITOR_FILE => "C:\Designs\kc705_kcpsm6_xadc\xadc_sim_values.txt")

 

I discovered that a good way to know if the file is being read by the simulator is to deliberately make a mistake in the header line of the stimulus file. For example…

 

TIME TEMP MY_MISTAKE VCCINT

 

… will result in the simulator generating and error message when parsing the file.

 

 

Secondly, there are rules for the stimulus file which are as follows…

 

Comments on lines starting with //

First active line is the header line.

Valid column names are: TIME TEMP VCCINT VCCAUX VCCBRAM VCCPINT VCCPAUX VCCDDRO VP VN VAUXP[0] VAUXN[0] VAUXP[1] VAUXN[1] etc

TIME must be in first column and must be an integer number of nano-seconds (e.g. 1050).

Analogue values must be 'real' and contain a decimal point (e.g. 0.0 and 3.4).

Each line including header line must not have extra spaces after the last character or digit.

Each data line must have same number of columns as the header line.

 

Here is an example that I created to use with the ‘KC705_KCPSM6_XADC_reference_design’ provided with the KCPMS6 version of PicoBlaze (available from http://www.xilinx.com/ipcenter/processor_central/picoblaze/member/ )…

 

TIME     VP   VN   VAUXP[0] VAUXN[0] VAUXP[8] VAUXN[8] TEMP   VCCINT VCCAUX VCCBRAM

0000000   0.1  0.0  0.0      0.0      0.9      0.0      20.0   0.97   1.78   0.98

1000000   0.2  0.0  0.1      0.0      0.8      0.0      30.0   0.98   1.79   0.99

2000000   0.3  0.0  0.2      0.0      0.7      0.0      40.0   0.99   1.80   1.00

3000000   0.4  0.0  0.3      0.0      0.6      0.0      50.0   1.00   1.81   1.01

4000000   0.5  0.0  0.4      0.0      0.5      0.0      60.0   1.01   1.82   1.02

5000000   0.6  0.0  0.5      0.0      0.4      0.0      70.0   1.02   1.83   1.03

 

 

Finally, the one that caught me out the longest and has clearly caught others out as well; it may take a LONG time for values to start appearing when reading XADC. In my case I found it took over 3.4ms seconds of simulation time (which was nearly 700,000 clock cycles in my design) before I saw a non-zero value being read. Furthermore, the value that I observed being read didn’t even correspond with any of the values in my stimulus file. After much head scratching I realised that the reason for this was the way I had enabled XADC to average 256 samples. A case of the XADC simulation model being correct but, as a result, not being suitable for a quick simulation. As soon as I disabled sample averaging (some bits defined by ‘INIT_40’) and run my simulation again, XADC rapidly generated values that correlated with the analogue values and times defined in my analogue stimulus file. Note that there is still a short delay before the values can be read from XADC but this consistent with the sample rate and multi-channel nature of XADC and the model correctly reflecting that.

Ken Chapman
Principal Engineer, Xilinx UK
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Teacher
Teacher
11,588 Views
Registered: ‎07-09-2009

When you created the xadc in the gui,

   what did you set the file seectin to  ?

      I seem to have the options 

       default, relative cvs or txt

 

I seem to only have the option of specifying a file location with the relative option

 

vivado 2015.4. 

 

 

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Xilinx Employee
Xilinx Employee
11,576 Views
Registered: ‎09-05-2007

In my case I instantiated the XADC primitive in my HDL code. I provided a link to the PicoBlaze lounge if you would like to look at the code.

Ken Chapman
Principal Engineer, Xilinx UK
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Visitor
Visitor
8,432 Views
Registered: ‎01-17-2017

More Details:

When you generate the XADC Core with GUI-Coregen, theen you can use DRP or AXI. When you choose DRP, then you get

 

SIM_MONITOR_FILE => "design.txt"

in the xadc_wiz_0.vhd in

\Project\Project.srcs\sources_1\ip\xadc_wiz_0\

Folder. design.txt is in the same folder, so the Path at SIM_MONITOR_FILE is relative to this folder.

But when you choose AXI and not DRP, there is no SIM_MONITOR_FILE, there suddenly is C_SIM_MONITOR_FILE, and the path there is relative to

\Project\Project.sim\sim_1\behav\
Folder. So you habe to put the design.txt there as

\Project\Project.sim\sim_1\behav\design.txt

and write in

\Project\Project.srcs\sources_1\ip\xadc_wiz_0\xadc_wiz_0.vhd
the line:
C_SIM_MONITOR_FILE      => "design.txt"

But ... if you simulate again, \Project\Project.sim\sim_1\behav\design.txt gets deleted. So you seek for another solution to just change the Path to the File.

 

You notice, that when you let Coregen build, there are two commands being executet:

set_property -dict [list CONFIG.SIM_FILE_SEL {Relative_path} CONFIG.SIM_FILE_REL_PATH {./Project.srcs/sources_1/ip/xadc_wiz_0/}] [get_ips xadc_wiz_0]
generate_target all [get_files  D:/Project/Project.srcs/sources_1/ip/xadc_wiz_0/xadc_wiz_0.xci]

But the first command tests if the design.txt is present at given path. The bug here is: It sees the path relative to the project main folder, but not relative to the simulation folder \Project\Project.sim\sim_1\behav\ where the Simulation searches.

So ... you cannot set the path via this command because the test fails or if the test passes, the simulation will not find the file. Changing C_SIM_MONITOR_FILE in xadc_wiz_0.vhd changes nothing. So ... very bad documented and very inconsistend behavior between XADC with DRP and AXI.

 

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Teacher
Teacher
8,419 Views
Registered: ‎07-09-2009

Thanks for that

 

I gave up....

 

It was so frustrating that I designed out the XADC...

 

it was easier and quicker to dump a SPI ADC on the board, ..

 

Sorry, I'm mainly involved in low volume , fast turn around designs, and the Xilinx tools are just leaving me behind, aimed at the big boys doing TCL based designs...

 

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Visitor
Visitor
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Registered: ‎01-17-2017

Solved! Just add the design.txt in VIVADO as simulation source.

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Teacher
Teacher
5,659 Views
Registered: ‎07-09-2009
Obvious, but I missed it... Well found..
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Observer
Observer
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Registered: ‎12-28-2017

design.pngHii,

 

I had make a microblaze based  AXILite ADC design which transfer data through Ethernet via TCP protocol. in SDK I have modified  the echo server example code and transfer data frequently, till now everything works good, but when I am plotting this data using MATLAB tool ( ex. sine wave as input )  my real time graph for low frequency (upto 250 Hz) coming good but above this it became distorted and gives very unusual plot. 

I am attaching my plot and vivado design , please any one can suggest me what may be the reason for this or why I am getting like this output. 

please suggest  my mail ID IS : shubham.dwivedi@eiwave.com

  low_freq.pnghigh_freq.pngaddress_editor.png

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