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vtupikov
Observer
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Registered: ‎06-11-2015

XELAB 2019.2 elaboration fails for simple UVM example design

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I am trying to simulate an example design (which is simulatable in Questa 10.6d+) in Vivado 2019.2 with use of batch mode on Win10. The design parsing goes ok:

         call  xvlog --sv -L uvm  *.sv
 

Though when trying to elaborate and generate design snapshot

         call  xelab -debug  all  work.hdl_top  -L uvm  -s    hdl_top
 

I am getting an error:

xsim.dir/hdl_top/obj/xsim_10.win64.obj:xsim_10.c:(.text+0x87b): undefined reference to `uvm_hdl_deposit'
xsim.dir/hdl_top/obj/xsim_10.win64.obj:xsim_10.c:(.text+0x994): undefined reference to `uvm_hdl_read'
xsim.dir/hdl_top/obj/xsim_10.win64.obj:xsim_10.c:(.text+0xa9a): undefined reference to `uvm_dpi_get_next_arg_c'
xsim.dir/hdl_top/obj/xsim_10.win64.obj:xsim_10.c:(.text+0xb57): undefined reference to `uvm_dpi_get_tool_name_c'
xsim.dir/hdl_top/obj/xsim_10.win64.obj:xsim_10.c:(.text+0xc14): undefined reference to `uvm_dpi_get_tool_version_c'
xsim.dir/hdl_top/obj/xsim_10.win64.obj:xsim_10.c:(.text+0xcec): undefined reference to `uvm_dpi_regcomp'
xsim.dir/hdl_top/obj/xsim_10.win64.obj:xsim_10.c:(.text+0xdd0): undefined reference to `uvm_dpi_regexec'
xsim.dir/hdl_top/obj/xsim_10.win64.obj:xsim_10.c:(.text+0xea0): undefined reference to `uvm_dpi_regfree'
xsim.dir/hdl_top/obj/xsim_10.win64.obj:xsim_10.c:(.text+0xf84): undefined reference to `uvm_re_match'
xsim.dir/hdl_top/obj/xsim_10.win64.obj:xsim_10.c:(.text+0x1065): undefined reference to `uvm_glob_to_re'
collect2.exe: error: ld returned 1 exit status
ERROR: [XSIM 43-3238] Failed to link the design.

Unfortunately neither UG900 nor Forum are helpful to troubleshoot the issue. I am attaching the archive with the project and batch file for expert's review. Thanks.

 

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bandi
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Registered: ‎09-15-2016

Hi @vtupikov ,

Glad that the issue got solved. Can you please close this thread by marking the post which helped as accepted solution.

Thanks & Regards,
Sravanthi B
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vtupikov
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Registered: ‎06-11-2015

Still hoping to get answer from Xilinx on the issue...

Thanks,

Vitali

 

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dprasad
Xilinx Employee
Xilinx Employee
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Registered: ‎09-13-2014

Seems like while compiling through "*.sv", you are compiling xlnx_uvm_package.sv as well. You don't need that, please remove that file and post that, it should work.

 

-dhiRAj

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vtupikov
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Registered: ‎06-11-2015

1. The design doesn't have any explicit import of xlnx_uvm_package.sv module, so I would appreciate if you could clarify how the package can be removed from compiling.

2. I gave it a try and built the unchanged design under Vivado 2020.1.  This time it passed elaboration stage thought "hang" during xsimk execution:

        a) the Win10 test-monitor shows that xsimk is wasting 40% of CPU power without

             reporting anything on the screen for more than 20 minutes until was killed.

         b) Below is the tool's dump:


C:\TEMP\01_uvm_vif_config_bd\tb>call xvlog --sv -L uvm sfr_if.sv
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/TEMP/01_uvm_vif_config_bd/tb/sfr_if.sv" into library work
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/TEMP/01_uvm_vif_config_bd/tb/sfr_agent_pkg.sv" into library work
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/TEMP/01_uvm_vif_config_bd/tb/sfr_test_pkg.sv" into library work
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/TEMP/01_uvm_vif_config_bd/tb/sfr_dut.sv" into library work
INFO: [VRFC 10-311] analyzing module sfr_dut
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/TEMP/01_uvm_vif_config_bd/tb/hdl_top.sv" into library work
INFO: [VRFC 10-311] analyzing module hdl_top
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/TEMP/01_uvm_vif_config_bd/tb/hvl_top.sv" into library work
INFO: [VRFC 10-311] analyzing module hvl_top
Vivado Simulator 2020.1
Copyright 1986-1999, 2001-2020 Xilinx, Inc. All Rights Reserved.
Running: C:/Xilinx/Vivado/2020.1/bin/unwrapped/win64.o/xelab.exe -debug all work.hdl_top -L uvm -s hdl_top
Multi-threading is on. Using 2 slave threads.
Starting static elaboration
Pass Through NonSizing Optimizer
Completed static elaboration
Starting simulation data flow analysis
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling package uvm.uvm_pkg
Compiling package std.std
Compiling module work.sfr_if
Compiling module work.sfr_dut
Compiling module work.hdl_top
Built simulation snapshot hdl_top

****** Webtalk v2020.1 (64-bit)
**** SW Build 2902540 on Wed May 27 19:54:49 MDT 2020
**** IP Build 2902112 on Wed May 27 22:43:36 MDT 2020
** Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.

source C:/TEMP/01_uvm_vif_config_bd/tb/xsim.dir/hdl_top/webtalk/xsim_webtalk.tcl -notrace
INFO: [Common 17-206] Exiting Webtalk at Wed Jun 10 06:47:32 2020...

****** xsim v2020.1 (64-bit)
**** SW Build 2902540 on Wed May 27 19:54:49 MDT 2020
**** IP Build 2902112 on Wed May 27 22:43:36 MDT 2020
** Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.

source xsim.dir/hdl_top/xsim_script.tcl
# xsim {hdl_top} -wdb {simulate_xsim.wdb} -autoloadwcfg -runall
Vivado Simulator 2020.1
Time resolution is 1 ps
run -all
UVM_INFO /proj/xbuilds/SWIP/2020.1_0223_2001/installs/lin64/Vivado/2020.1/data/system_verilog/uvm_1.2/xlnx_uvm_package.sv(18601) @ 0: reporter [UVM/RELNOTES]
(Specify +UVM_NO_RELNOTES to turn off this notice)
with `UVM_OBJECT_DO_NOT_NEED_CONSTRUCTOR undefined.

You are using a version of the UVM library that has been compiled
with `UVM_NO_DEPRECATED undefined.

You are using a version of the UVM library that has been compiled

*********** IMPORTANT RELEASE NOTES ************
----------------------------------------------------------------
(C) 2013-2014 NVIDIA Corporation
(C) 2011-2013 Cypress Semiconductor Corp.
(C) 2006-2014 Synopsys, Inc.
(C) 2007-2014 Cadence Design Systems, Inc.
(C) 2007-2014 Mentor Graphics Corporation


----------------------------------------------------------------

 

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ranganat
Xilinx Employee
Xilinx Employee
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Registered: ‎07-03-2018

1. Remove compiling xlxnx_uvm_package.sv file from compile list.

2. Able to run the test-case in windows using vivado 2020.1. Add below settings while running test-case.

 set_property -name {xsim.compile.xvlog.more_options} -value {-L UVM} -objects [get_filesets sim_1]

set_property -name {xsim.simulate.runtime} -value {-all} -objects [get_filesets sim_1]

set_property -name {xsim.simulate.xsim.more_options} -value {-testplusarg UVM_TESTNAME=sfr_test} -objects [get_filesets sim_1]

set_property -name {xsim.elaborate.xelab.more_options} -value {-L UVM} -objects [get_filesets sim_1]

Run behavioral simulation (using launch_simulation).

Please find below simulation log file info :

 

UVM_INFO /proj/xbuilds/SWIP/2020.1_0223_2001/installs/lin64/Vivado/2020.1/data/system_verilog/uvm_1.2/xlnx_uvm_package.sv(18648) @ 0: reporter [NO_DPI_TSTNAME] UVM_NO_DPI defined--getting UVM_TESTNAME directly, without DPI
UVM_INFO @ 0: reporter [RNTST] Running test sfr_test...
UVM_INFO /proj/xbuilds/SWIP/2020.1_0223_2001/installs/lin64/Vivado/2020.1/data/system_verilog/uvm_1.2/xlnx_uvm_package.sv(20867) @ 0: reporter [UVM/COMP/NAMECHECK] This implementation of the component name checks requires DPI to be enabled
UVM_INFO /proj/xbuilds/SWIP/2020.1_0223_2001/installs/lin64/Vivado/2020.1/data/system_verilog/uvm_1.2/xlnx_uvm_package.sv(19968) @ 81970000: reporter [TEST_DONE] 'run' phase is ready to proceed to the 'extract' phase
UVM_INFO ../../../../../sfr_scoreboard.svh(75) @ 81970000: uvm_test_top.env.sb [** UVM TEST PASSED **] SFR agent test passed with no errors in 800 valid read scenarios
UVM_INFO /proj/xbuilds/SWIP/2020.1_0223_2001/installs/lin64/Vivado/2020.1/data/system_verilog/uvm_1.2/xlnx_uvm_package.sv(13673) @ 81970000: reporter [UVM/REPORT/SERVER] [UVM/RELNOTES] 1
[UVM/COMP/NAMECHECK] 1
[TEST_DONE] 1
[RNTST] 1
[NO_DPI_TSTNAME] 1
[** UVM TEST PASSED **] 1
** Report counts by id
UVM_FATAL : 0
UVM_ERROR : 0
UVM_WARNING : 0
UVM_INFO : 6
** Report counts by severity

--- UVM Report Summary ---

 

Please find the attached test-case zip folder (test-case run with no issues).

Please let us know for further details if required.



 

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vtupikov
Observer
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Registered: ‎06-11-2015

I confirm that project mode design is simulate-able in Vivado 2020.1 after applying set_property corrections as listed in ranganat's response section 2. The removal of xlxnx_uvm_package.sv file (response's section 1) is not required for that.

Though the original question was for batch mode (non project mode), at this point I am ok with work around.

Thank you.

 

 

 

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ranganat
Xilinx Employee
Xilinx Employee
1,429 Views
Registered: ‎07-03-2018

Please find below are commands to run in batch mode.

call xvlog -sv -L uvm sfr_if.sv sfr_agent_pkg.sv sfr_test_pkg.sv sfr_dut.sv hdl_top.sv hvl_top.sv
call xelab hvl_top -relax -s top -L uvm 
call xsim top -testplusarg UVM_TESTNAME=sfr_test -runall

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vtupikov
Observer
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Registered: ‎06-11-2015

Awsome !! Finally we got it working!!!

The only change I had to apply on my end for call xsim line was " " as shown below:

call xsim top -testplusarg "UVM_TESTNAME=sfr_test" -runall

Thank you, ranganat.

 

 

bandi
Moderator
Moderator
1,266 Views
Registered: ‎09-15-2016

Hi @vtupikov ,

Glad that the issue got solved. Can you please close this thread by marking the post which helped as accepted solution.

Thanks & Regards,
Sravanthi B
----------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful and reply oriented.
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