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Observer
Observer
912 Views
Registered: ‎05-11-2018

XSIM Verilog replication operator with zero produces incorrect values

When using replication operator the Vivado simulator produces incorrect values quietly without generating a warning or error.

 

module test(

    );
    
    wire [3:0] a = 'b1;
    wire [3:0] b;
    
    assign b = {a,{0{1'b0}}};
 
    initial begin
        #1;
        $display("b is %d",b); 
    end
    
endmodule

 

Vivado Simulator 2018.2
Time resolution is 1 ps
b is  2

 

Same result I got with 2017.4

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Xilinx Employee
Xilinx Employee
900 Views
Registered: ‎08-10-2015

Hi @ronagyl_adi,

 

 

Issue  been reported tp factory.

 

 

Thanks,

Sunilkumar

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Scholar
Scholar
780 Views
Registered: ‎09-16-2009

A little late to this thread, however please note that a zero replication count is entirely legal within the language - as long as it appears in a concatenation -as your example does.

 

The example above should not produce an error nor warning.  The resulting value of variable b should be 4'd1.  So the problem with XSIM is it produces the wrong value.

 

Regards,

 

Mark

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