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Observer seb.mitchison
Observer
280 Views
Registered: ‎03-15-2018

Xilinx CAN FD IP core doesn't simulate PG223

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Hi,

This question relates to the CAN IP core in PG223.

I haven't had any issues I couldn’t solve (so far) in integrating the CAN IP into my design, place and routing it and working with it on the hardware.

I am having difficulty in simulating it though. I can generate and simulate the example design fine, but when I try to simulate my 'core' system testbench that includes the CAN FD IP core it fails to get into the Vivado simulator.

‘ERROR: [XSIM 43-4025] ".../can/design/ip/canfd/sim/canfd.v" Line 122. The number of actual scalars 2, is not the same as number of formal scalars 32, for aggregate net s_axi_rdata.’

I attach the verilog file in question, 

My 2018.2 Vivado project is configured for:

Target language - VHDL

Simulator language - Mixed

I have seen this article but wasn't sure this was the solution... https://www.xilinx.com/support/answers/68055.html

Cheers,
Seb

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Observer seb.mitchison
Observer
228 Views
Registered: ‎03-15-2018

Re: Xilinx CAN FD IP core doesn't simulate PG223

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Answering in case it helps others.

Original port mapping:

-- instantiate num_of_can_g instances of the Xilinx AXI CAN (FD) component
gen_canfd : for i in 0 to num_of_can_g - 1 generate
canfd_gen : canfd
port map(
can_clk => can_clk,
can_phy_tx => cano.txd(i),
can_phy_rx => cani.rxd(i),
ip2bus_intrevent => cano.int(i),
s_axi_aclk => clk,
s_axi_aresetn => reset_l,
s_axi_awaddr => std_logic_vector(axi_can_m2s(i).awaddr(12 downto 0)),
s_axi_awvalid => axi_can_m2s(i).awvalid,
s_axi_awready => axi_can_s2m(i).awready,
s_axi_wdata => std_logic_vector(axi_can_m2s(i).wdata),
s_axi_wvalid => axi_can_m2s(i).wvalid,
s_axi_wready => axi_can_s2m(i).wready,
unsigned(s_axi_bresp) => axi_can_s2m(i).bresp,
s_axi_bvalid => axi_can_s2m(i).bvalid,
s_axi_bready => axi_can_m2s(i).bready,
s_axi_araddr => std_logic_vector(axi_can_m2s(i).araddr(12 downto 0)),
s_axi_arvalid => axi_can_m2s(i).arvalid,
s_axi_arready => axi_can_s2m(i).arready,
unsigned(s_axi_rdata) => axi_can_s2m(i).rdata,
unsigned(s_axi_rresp) => axi_can_s2m(i).rresp,
s_axi_rvalid => axi_can_s2m(i).rvalid,
s_axi_rready => axi_can_m2s(i).rready
);
end generate gen_canfd;

We had to specify on the VHDL port mapping where we isntantiated the core: "unsigned(s_axi_rdata) => axi_can_s2m(i).rdata(31 downto 0)," even though our record was (31 downto 0). Possibly would have seen this error on araddr as well had our record not been (39 downto 0) forcing us to assign only (12 downto 0).

Wierd bug but it simulates now.

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1 Reply
Observer seb.mitchison
Observer
229 Views
Registered: ‎03-15-2018

Re: Xilinx CAN FD IP core doesn't simulate PG223

Jump to solution

Answering in case it helps others.

Original port mapping:

-- instantiate num_of_can_g instances of the Xilinx AXI CAN (FD) component
gen_canfd : for i in 0 to num_of_can_g - 1 generate
canfd_gen : canfd
port map(
can_clk => can_clk,
can_phy_tx => cano.txd(i),
can_phy_rx => cani.rxd(i),
ip2bus_intrevent => cano.int(i),
s_axi_aclk => clk,
s_axi_aresetn => reset_l,
s_axi_awaddr => std_logic_vector(axi_can_m2s(i).awaddr(12 downto 0)),
s_axi_awvalid => axi_can_m2s(i).awvalid,
s_axi_awready => axi_can_s2m(i).awready,
s_axi_wdata => std_logic_vector(axi_can_m2s(i).wdata),
s_axi_wvalid => axi_can_m2s(i).wvalid,
s_axi_wready => axi_can_s2m(i).wready,
unsigned(s_axi_bresp) => axi_can_s2m(i).bresp,
s_axi_bvalid => axi_can_s2m(i).bvalid,
s_axi_bready => axi_can_m2s(i).bready,
s_axi_araddr => std_logic_vector(axi_can_m2s(i).araddr(12 downto 0)),
s_axi_arvalid => axi_can_m2s(i).arvalid,
s_axi_arready => axi_can_s2m(i).arready,
unsigned(s_axi_rdata) => axi_can_s2m(i).rdata,
unsigned(s_axi_rresp) => axi_can_s2m(i).rresp,
s_axi_rvalid => axi_can_s2m(i).rvalid,
s_axi_rready => axi_can_m2s(i).rready
);
end generate gen_canfd;

We had to specify on the VHDL port mapping where we isntantiated the core: "unsigned(s_axi_rdata) => axi_can_s2m(i).rdata(31 downto 0)," even though our record was (31 downto 0). Possibly would have seen this error on araddr as well had our record not been (39 downto 0) forcing us to assign only (12 downto 0).

Wierd bug but it simulates now.

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