UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Newbie th.birjit
Newbie
302 Views
Registered: ‎05-20-2019

Xilinx Vivado Simulation

Jump to solution

d[7:0] is an input vector, which shows to be ZZ in the simulation waveform. When does such a situation arise in a Xilinx Vivado simulation ? What mistake I might have made which is resulting in this error ?1.PNG

0 Kudos
1 Solution

Accepted Solutions
Highlighted
Adventurer
Adventurer
291 Views
Registered: ‎06-28-2018

Re: Xilinx Vivado Simulation

Jump to solution

Z means high impedance. It means d[7:0] has no driver.

View solution in original post

3 Replies
Highlighted
Adventurer
Adventurer
292 Views
Registered: ‎06-28-2018

Re: Xilinx Vivado Simulation

Jump to solution

Z means high impedance. It means d[7:0] has no driver.

View solution in original post

Xilinx Employee
Xilinx Employee
215 Views
Registered: ‎07-11-2019

Re: Xilinx Vivado Simulation

Jump to solution

Hello @th.birjit 

Would you be able to provide the source code of the design and the testbench code, so that I may see why you are getting the high impedance output? 

X = Unknown Value -> there could be multiple outputs assigned to s[7:0] causing this unknown value.

Z = Tri-state or High impedance, like mentioned by @baltintop  -> There is another signal that will pull the signal high or low. Usually what causes this error is conditional statements that do not cover all of the cases, so the output becomes a known state of "High Impedance", but I cannot be sure until I see the code. 

I have also attached a firum post that also resulted in a high impedance output that may be similar to your situation/code. 

Forum: https://forums.xilinx.com/t5/Simulation-and-Verification/High-Impedance-Output-in-Simulation-of-A-Simple-Verilog-Code/td-p/930681

I hope this helps clarify things, and if it does not completely help, please let me know and we can work on a solution together! 

-------------------------------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------------------------------

 

Newbie th.birjit
Newbie
144 Views
Registered: ‎05-20-2019

Re: Xilinx Vivado Simulation

Jump to solution

Thank you.

0 Kudos