We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

Showing results for 
Search instead for 
Did you mean: 
Visitor jg_spitfire
Registered: ‎12-10-2019

base zynq example does not simulate all signals


Hi, I am using this tutorial How to use the Zynq-7000 Verification IP to Verify and Debug Using Simulation and in tcl terminal I get "AXI VIP Test PASSED" but not all signals are generated (as shown in the image), why?, I am using vivado 2018.2 in windows 10 home, thanks



0 Kudos
1 Reply
Xilinx Employee
Xilinx Employee
Registered: ‎07-11-2019

Re: base zynq example does not simulate all signals

Hello @jg_spitfire 

I believe the signals you are looking for can be found by going to the "scope" tab on the left and expanding the tabs in the "zynq_sys". When you have found a signal, or set of signals, you would like to watch in the waveform, right click on it and select "add to wave window". This will add the signal to the waveform. 

I hope this helps! 

Don’t forget to reply, kudo, and accept as solution.

0 Kudos