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Visitor jg_spitfire
Visitor
156 Views
Registered: ‎12-10-2019

base zynq example does not simulate all signals

 

Hi, I am using this tutorial How to use the Zynq-7000 Verification IP to Verify and Debug Using Simulation and in tcl terminal I get "AXI VIP Test PASSED" but not all signals are generated (as shown in the image), why?, I am using vivado 2018.2 in windows 10 home, thanks

Untitled.jpg

 

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Xilinx Employee
Xilinx Employee
89 Views
Registered: ‎07-11-2019

Re: base zynq example does not simulate all signals

Hello @jg_spitfire 

I believe the signals you are looking for can be found by going to the "scope" tab on the left and expanding the tabs in the "zynq_sys". When you have found a signal, or set of signals, you would like to watch in the waveform, right click on it and select "add to wave window". This will add the signal to the waveform. 

I hope this helps! 

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