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738 Views
Registered: ‎06-01-2016

block ram inference problem during simulation

 

The following message is shown on simulation  in Vivado2015.3

 

 

ERROR: [VRFC 10-2063] Module <design_1_blk_mem_gen_0_0> not found while processing module instance

<blk_mem_gen_0> [/home/rajesh/seq_detect/seq_detect.ip_user_files/bd/design_1/hdl/design_1.v:40]


ERROR: [XSIM 43-3322] Static elaboration of top level Verilog design unit(s) in library work failed.

 

Help me

 

Thanks
- Rajesh Kr Meena
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Moderator
Moderator
732 Views
Registered: ‎01-16-2013

Re: block ram inference problem during simulation

Hi,

Refer https://www.xilinx.com/support/answers/56492.html
Also check the source hierarchy and see if the files associated with this module is present under simulation source or not.


Thanks,
Yash

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Xilinx Employee
Xilinx Employee
716 Views
Registered: ‎08-01-2008

Re: block ram inference problem during simulation

can you please share test case. You can try with Global synthesis option in place of OOC synthesis
Thanks and Regards
Balkrishan
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