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Observer yongbyb2000
Observer
9,564 Views
Registered: ‎08-23-2008

can vivado generate verilog IPCORE simulation file?

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I use vivado generate 3 IPcore in my project, one is PLL, one is FIFO,one is RAM,but when i want to simulate my project i found the PLL files are verilog and the others are VHDL. I choose verilog language in my project, can I generate all IPcore in verilog language? how can i do it?

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Xilinx Employee
Xilinx Employee
18,439 Views
Registered: ‎09-20-2012

Re: can vivado generate verilog IPCORE simulation file?

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Hi @yongbyb2000

 

In Vivado 2015.3, 2015.4 the FIFO generator, block memory generator IP's deliver only VHDL simulation model irrespective of project settings. We are planning to deliver verilog model in our upcoming release vivado 2016.1. 

Thanks,
Deepika.
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Xilinx Employee
Xilinx Employee
18,440 Views
Registered: ‎09-20-2012

Re: can vivado generate verilog IPCORE simulation file?

Jump to solution

Hi @yongbyb2000

 

In Vivado 2015.3, 2015.4 the FIFO generator, block memory generator IP's deliver only VHDL simulation model irrespective of project settings. We are planning to deliver verilog model in our upcoming release vivado 2016.1. 

Thanks,
Deepika.
--------------------------------------------------------------------------------------------
Google your question before posting. If someone's post answers your question, mark the post as answer with "Accept as solution". If you see a particularly good and informative post, consider giving it Kudos (the star on the left)
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Observer yongbyb2000
Observer
9,530 Views
Registered: ‎08-23-2008

Re: can vivado generate verilog IPCORE simulation file?

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OK,thanks
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Newbie vijayxilinx
Newbie
1,442 Views
Registered: ‎02-22-2018

Re: can vivado generate verilog IPCORE simulation file?

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Hi Deepika,

 

Iam using Vivado v2016.3 (64-bit), but still iam not able to get verilog simulation files.

I have generated native FIFO and opened IP example design.

Simulation files in the Example Design are all vhdl files, and not sure how to generate verilog files.

Still there is no support for verilog in v2016.3?

 

Regards

Sunil Kumar

 

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Newbie vijayxilinx
Newbie
1,398 Views
Registered: ‎02-22-2018

Re: can vivado generate verilog IPCORE simulation file?

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Hi Deepika,

 

I have generated native FIFO and opened IP example design.

All the source files were VHDL files.

Iam using Vivado v2016.3 (64-bit), iam not able to get verilog source files.

 

Also the simulation files in the Example Design are all vhdl files, and not sure how to generate verilog files.

Still there is no support for verilog in v2016.3?

 

Regards

Sunil Kumar

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