compile Library "c_addsub_v12_0_10"

[urvish_panchal89]

I need library "c_addsub_v12_0_10" for Riviera-PRO simulator and for that I am running below command. It does not seem generating library "c_addsub_v12_0_10". I tried referencing "C:\Xilinx\vivado\2016.4\data\ip\xilinx\c_addsub_v12_0\hdl\c_addsub_v12_0_vh_rfs.vhd" in simulation, however it did not work. Can someone help me how to get it?

compile_simlib -force -language all -dir {C:/Aldec/Riviera-PRO-2016.06-x64/bin} -simulator riviera -simulator_exec_path {C:/Aldec/Riviera-PRO-2016.06-x64/bin} -library all -family  zynq

Thanks

[muzaffer]

@urvish_panchal89 this file is encrypted. Verify that your simulator can understand Xilinx encrypted sources.

[urvish_panchal89]

I am using Riviera-PRO simulation. It is giving me below error and similar for other libraries. Some of them went smooth(Not in bold), but for some(Bold) It is giving error. Am I missing something? I mapped all pre-compiled libraries before compiling these IPs.

COMP96 ERROR COMP96_0055: "Error in encrypted code." "C:\proj_work\workdir\design\iga\enc_sysgen\ip_Encoder30\ip_catalog\encoder.srcs\sources_1\bd\encoder_bd\ip\encoder_bd_encoder_1_0\encoder_c_addsub_v12_0_i0\hdl\c_addsub_v12_0_vh_rfs.vhd" 5249 92

COMP96 File: C:\proj_work\workdir\design\iga\enc_sysgen\ip_Encoder30\ip_catalog\encoder.srcs\sources_1\bd\encoder_bd\ip\encoder_bd_encoder_1_0\encoder_c_addsub_v12_0_i0\hdl\xbip_utils_v3_0_vh_rfs.vhd
COMP96 File: C:\proj_work\workdir\design\iga\enc_sysgen\ip_Encoder30\ip_catalog\encoder.srcs\sources_1\bd\encoder_bd\ip\encoder_bd_encoder_1_0\encoder_c_addsub_v12_0_i0\hdl\c_reg_fd_v12_0_vh_rfs.vhd
COMP96 File: C:\proj_work\workdir\design\iga\enc_sysgen\ip_Encoder30\ip_catalog\encoder.srcs\sources_1\bd\encoder_bd\ip\encoder_bd_encoder_1_0\encoder_c_addsub_v12_0_i0\hdl\xbip_dsp48_wrapper_v3_0_vh_rfs.vhd
COMP96 File: C:\proj_work\workdir\design\iga\enc_sysgen\ip_Encoder30\ip_catalog\encoder.srcs\sources_1\bd\encoder_bd\ip\encoder_bd_encoder_1_0\encoder_c_addsub_v12_0_i0\hdl\xbip_pipe_v3_0_vh_rfs.vhd
COMP96 File: C:\proj_work\workdir\design\iga\enc_sysgen\ip_Encoder30\ip_catalog\encoder.srcs\sources_1\bd\encoder_bd\ip\encoder_bd_encoder_1_0\encoder_c_addsub_v12_0_i0\hdl\xbip_dsp48_addsub_v3_0_vh_rfs.vhd
COMP96 ERROR COMP96_0055: "Error in encrypted code." "C:\proj_work\workdir\design\iga\enc_sysgen\ip_Encoder30\ip_catalog\encoder.srcs\sources_1\bd\encoder_bd\ip\encoder_bd_encoder_1_0\encoder_c_addsub_v12_0_i0\hdl\xbip_dsp48_addsub_v3_0_vh_rfs.vhd" 1247 63
COMP96 File: C:\proj_work\workdir\design\iga\enc_sysgen\ip_Encoder30\ip_catalog\encoder.srcs\sources_1\bd\encoder_bd\ip\encoder_bd_encoder_1_0\encoder_c_addsub_v12_0_i0\hdl\xbip_addsub_v3_0_vh_rfs.vhd
COMP96 ERROR COMP96_0055: "Error in encrypted code." "C:\proj_work\workdir\design\iga\enc_sysgen\ip_Encoder30\ip_catalog\encoder.srcs\sources_1\bd\encoder_bd\ip\encoder_bd_encoder_1_0\encoder_c_addsub_v12_0_i0\hdl\xbip_addsub_v3_0_vh_rfs.vhd" 458 63
COMP96 File: C:\proj_work\workdir\design\iga\enc_sysgen\ip_Encoder30\ip_catalog\encoder.srcs\sources_1\bd\encoder_bd\ip\encoder_bd_encoder_1_0\encoder_c_addsub_v12_0_i0\hdl\c_addsub_v12_0_vh_rfs.vhd
COMP96 ERROR COMP96_0055: "Error in encrypted code." "C:\proj_work\workdir\design\iga\enc_sysgen\ip_Encoder30\ip_catalog\encoder.srcs\sources_1\bd\encoder_bd\ip\encoder_bd_encoder_1_0\encoder_c_addsub_v12_0_i0\hdl\c_addsub_v12_0_vh_rfs.vhd" 5249 92

Thanks

[urvish_panchal89 · Accepted solution]

Understanding the generated third-party script by Vivado, gave me some hint to fix simulation flow in my script and thus I was able to resolve the errors.

Regards

[chaity@33]

Hi,

Can u just explain what was the reason of this error exactly and how did u resolve it ?

As i am also getting a similar kind of error and your experience can be helpful.