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Adventurer
Adventurer
3,052 Views
Registered: ‎02-06-2012

compile_simlib fails with Questa 10.6b and Vivado 2017.4

Hello,

 

I can't find a way to compile simulation libraries - looks like the problem is mostly with encrypted Verilog files, but I'm not sure if it's only that.

I use Questa 10.6b and Vivado 2017.4, but the same problem happens with I try with Vivado 2016.4

Vivado command:

compile_simlib -simulator questa -language all -dir compile_simlib -library all -family kintex7 -verbose

The most recurring error seems to be like this one:

 

-- Compiling module GTXE2_CHANNEL_FAST_WRAP
###### /<cut>/Vivado/2017.4/data/secureip/gtxe2_channel_fast/gtxe2_channel_fast_001.vp(486):  in protected region.
** Error: /<cut>/Xilinx/Vivado/2017.4/data/secureip/gtxe2_channel_fast/gtxe2_channel_fast_001.vp(486): (vlog-2163) Macro `<protected> is undefined

I see literally hundreds of such errors, see attached logs - I've also attached all the files generated by Vivado for secureip library (for better debugging info).

 

I saw a few very similar topics in these forums regarding compile_simlib problems. Previous speakers (posters?) were shot down with a "use supported Questa version" remark, but I do have supported version and still encounter problems.

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14 Replies
Adventurer
Adventurer
3,048 Views
Registered: ‎02-06-2012

Re: compile_simlib fails with Questa 10.6b and Vivado 2017.4

P.S. I've also played with some tweaks like changing target family, but none of this helps.
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Moderator
Moderator
3,041 Views
Registered: ‎09-15-2016

Re: compile_simlib fails with Questa 10.6b and Vivado 2017.4

HI @abyszuk,

 

Can you please try compiling the libraries using the below command which includes simulator_exec_path option and check if it helps.

 

compile_simlib -simulator questa -simulator_exec_path {<path_to_questa>/questa/10.6b/bin} -family all -language all -library all -dir {<path_to_compile_libraries>/compile_simlib} -verbose 

 

 

Thanks & Regards,

Sravanthi B

 

Thanks & Regards,
Sravanthi B
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Adventurer
Adventurer
3,026 Views
Registered: ‎02-06-2012

Re: compile_simlib fails with Questa 10.6b and Vivado 2017.4

HI @bandi,

I've run the command as you asked and it didn't help.
Which IMHO isn't surprising - Vivado can pick up correct paths for Questa, it's that vlog complains about content of simulation libraries.
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Adventurer
Adventurer
2,964 Views
Registered: ‎02-06-2012

Re: compile_simlib fails with Questa 10.6b and Vivado 2017.4

Today I've tried another thing, with the same failure.

I've opened Questa GUI and tried to manually compile some of the offending secureip files.

For example I've typed in the Questa TCL console:

vlog -64 -work xil_defaultlib /home/adrian/opt/Xilinx/Vivado/2016.4/data/secureip/gtxe2_channel/gtxe2_channel_001.vp

But I get exactly the same errors as mentioned in previous posts:

# -- Compiling module GTXE2_CHANNEL_WRAP
# ** Error: /home/adrian/opt/Xilinx/Vivado/2016.4/data/secureip/gtxe2_channel/gtxe2_channel_001.vp(471): (vlog-2163) Macro `<protected> is undefined.
# ** Error: /home/adrian/opt/Xilinx/Vivado/2016.4/data/secureip/gtxe2_channel/gtxe2_channel_001.vp(471): (vlog-2163) Macro `<protected> is undefined.
# ** Error: /home/adrian/opt/Xilinx/Vivado/2016.4/data/secureip/gtxe2_channel/gtxe2_channel_001.vp(471): (vlog-2163) Macro `<protected> is undefined.
# ** Error: /home/adrian/opt/Xilinx/Vivado/2016.4/data/secureip/gtxe2_channel/gtxe2_channel_001.vp(471): (vlog-2163) Macro `<protected> is undefined.
# ** Error: (vlog-13032) /home/adrian/opt/Xilinx/Vivado/2016.4/data/secureip/gtxe2_channel/gtxe2_channel_001.vp(471): syntax error in protected region.
# 
# ** Error: /home/adrian/opt/Xilinx/Vivado/2016.4/data/secureip/gtxe2_channel/gtxe2_channel_001.vp(471): (vlog-2163) Macro `<protected> is undefined.
# ** Error: /home/adrian/opt/Xilinx/Vivado/2016.4/data/secureip/gtxe2_channel/gtxe2_channel_001.vp(471): (vlog-2163) Macro `<protected> is undefined.
# ** Error: /home/adrian/opt/Xilinx/Vivado/2016.4/data/secureip/gtxe2_channel/gtxe2_channel_001.vp(471): (vlog-2163) Macro `<protected> is undefined.
# ** Error: /home/adrian/opt/Xilinx/Vivado/2016.4/data/secureip/gtxe2_channel/gtxe2_channel_001.vp(471): (vlog-2163) Macro `<protected> is undefined.
# ** Error: (vlog-13069) /home/adrian/opt/Xilinx/Vivado/2016.4/data/secureip/gtxe2_channel/gtxe2_channel_001.vp(471): syntax error in protected region.

I've also tried changing compile options like Verilog version or switching to SystemVerilog but it didn't change anything.

 

What the hell? o_O

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Xilinx Employee
Xilinx Employee
2,907 Views
Registered: ‎07-16-2008

Re: compile_simlib fails with Questa 10.6b and Vivado 2017.4

This is not reproducible at my end.

When you launched compile_simlib command, did you have an existing modelsim.ini in the target directory, or did you have $MODELSIM environment variable to point to a specific modelsim.ini?

I see the following message printed in the compile_simlib.log.

vmap secureip /home/adrian/syncthing/praca/elka/CBM/wzab/DPB_design/project/stsDPB_simpleMS/sim/top_tb_cosim/compile_simlib/secureip
Modifying modelsim.ini

 

Please ensure no modelsim.ini exists in the target directory or pointed to by $MODELSIM and try again. This will allow the modelsim.ini in the 10.6b install directory to be copied to the target directory and edited accordingly.

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Adventurer
Adventurer
2,888 Views
Registered: ‎02-06-2012

Re: compile_simlib fails with Questa 10.6b and Vivado 2017.4

Hello @graces,

 

This was a modelsim.ini left after previous 'compile_simlib' invocations, so it was touched only by Vivado.

Nevertheless, I've already tried doing what you propose (and did that again just to be sure) but the result is still the same.

 

I can't figure this out - it was some time since I've had to use secureip, but surely this worked just fine with previous Vivado/Questa versions (around 2014.4 and Questa 10.5)

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Xilinx Employee
Xilinx Employee
2,880 Views
Registered: ‎07-16-2008

Re: compile_simlib fails with Questa 10.6b and Vivado 2017.4

This is really strange.

When you opened Modelsim GUI standalone and tried to manually compile the secureip sources, did you leave any modelsim.ini in the current directory?

Can you please attach the new compile_simlib.log?

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Adventurer
Adventurer
2,863 Views
Registered: ‎02-06-2012

Re: compile_simlib fails with Questa 10.6b and Vivado 2017.4

With standalone GUI operation I used modelsim.ini left over by previous compile_simlib run.

Attached new log - I've started compile_simlib without any modelsim.ini in a directory.

 

P.S. I always have to change file extension to .txt, because otherwise forums website throws the following error, which is pretty annoying.

Correct the highlighted errors and try again.
The attachment's compile_simlib.log content type (text/x-log) does not match its file extension and has been removed.

 

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Xilinx Employee
Xilinx Employee
2,852 Views
Registered: ‎07-16-2008

Re: compile_simlib fails with Questa 10.6b and Vivado 2017.4

Can you also attach modelsim.ini for a look?

Please try the standalone GUI operation with the default modelsim.ini inside the Modelsim install directory.

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Adventurer
Adventurer
2,285 Views
Registered: ‎02-06-2012

Re: compile_simlib fails with Questa 10.6b and Vivado 2017.4

modelsim.ini attached.

 

With the default modelsim.ini the result is still the same.

vlog -64 -work xil_defaultlib /home/adrian/opt/Xilinx/Vivado/2017.4/data/secureip/gtxe2_channel/gtxe2_channel_001.vp
# QuestaSim-64 vlog 10.6b Compiler 2017.05 May 25 2017
# Start time: 11:12:42 on Apr 10,2018
# vlog -reportprogress 300 -64 -work xil_defaultlib /home/adrian/opt/Xilinx/Vivado/2017.4/data/secureip/gtxe2_channel/gtxe2_channel_001.vp 
# -- Compiling module GTXE2_CHANNEL_WRAP
# ** Error: /home/adrian/opt/Xilinx/Vivado/2017.4/data/secureip/gtxe2_channel/gtxe2_channel_001.vp(486): (vlog-2163) Macro `<protected> is undefined.
# ** Error: /home/adrian/opt/Xilinx/Vivado/2017.4/data/secureip/gtxe2_channel/gtxe2_channel_001.vp(486): (vlog-2163) Macro `<protected> is undefined.
# ** Error: /home/adrian/opt/Xilinx/Vivado/2017.4/data/secureip/gtxe2_channel/gtxe2_channel_001.vp(486): (vlog-2163) Macro `<protected> is undefined.
# ** Error: /home/adrian/opt/Xilinx/Vivado/2017.4/data/secureip/gtxe2_channel/gtxe2_channel_001.vp(486): (vlog-2163) Macro `<protected> is undefined.
# ** Error: (vlog-13032) /home/adrian/opt/Xilinx/Vivado/2017.4/data/secureip/gtxe2_channel/gtxe2_channel_001.vp(486): syntax error in protected region.
# 
# ** Error: /home/adrian/opt/Xilinx/Vivado/2017.4/data/secureip/gtxe2_channel/gtxe2_channel_001.vp(486): (vlog-2163) Macro `<protected> is undefined.
# ** Error: /home/adrian/opt/Xilinx/Vivado/2017.4/data/secureip/gtxe2_channel/gtxe2_channel_001.vp(486): (vlog-2163) Macro `<protected> is undefined.
# ** Error: /home/adrian/opt/Xilinx/Vivado/2017.4/data/secureip/gtxe2_channel/gtxe2_channel_001.vp(486): (vlog-2163) Macro `<protected> is undefined.
# ** Error: (vlog-13069) /home/adrian/opt/Xilinx/Vivado/2017.4/data/secureip/gtxe2_channel/gtxe2_channel_001.vp(486): syntax error in protected region.
# 
# ** Error: /home/adrian/opt/Xilinx/Vivado/2017.4/data/secureip/gtxe2_channel/gtxe2_channel_001.vp(486): (vlog-13205) Syntax error found in the scope following '<protected>'. Is there a missing '::'?

Why is Questa complaining about undefined macro?

It looks like Questa can decrypt file just fine, but later fails to parse it.

Maybe this is some obscure bug in Questa, but triggered by Xilinx library?

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Adventurer
Adventurer
2,292 Views
Registered: ‎02-06-2012

Re: compile_simlib fails with Questa 10.6b and Vivado 2017.4

modelsim.ini attached.

 

With default .ini the result is as usual:

vlog -64 -work xil_defaultlib /home/adrian/opt/Xilinx/Vivado/2017.4/data/secureip/gtxe2_channel/gtxe2_channel_001.vp
# QuestaSim-64 vlog 10.6b Compiler 2017.05 May 25 2017
# Start time: 11:20:14 on Apr 10,2018
# vlog -reportprogress 300 -64 -work xil_defaultlib /home/adrian/opt/Xilinx/Vivado/2017.4/data/secureip/gtxe2_channel/gtxe2_channel_001.vp 
# -- Compiling module GTXE2_CHANNEL_WRAP
# ** Error: /home/adrian/opt/Xilinx/Vivado/2017.4/data/secureip/gtxe2_channel/gtxe2_channel_001.vp(486): (vlog-2163) Macro `<protected> is undefined.
# ** Error: /home/adrian/opt/Xilinx/Vivado/2017.4/data/secureip/gtxe2_channel/gtxe2_channel_001.vp(486): (vlog-2163) Macro `<protected> is undefined.
# ** Error: /home/adrian/opt/Xilinx/Vivado/2017.4/data/secureip/gtxe2_channel/gtxe2_channel_001.vp(486): (vlog-2163) Macro `<protected> is undefined.
# ** Error: /home/adrian/opt/Xilinx/Vivado/2017.4/data/secureip/gtxe2_channel/gtxe2_channel_001.vp(486): (vlog-2163) Macro `<protected> is undefined.
# ** Error: (vlog-13032) /home/adrian/opt/Xilinx/Vivado/2017.4/data/secureip/gtxe2_channel/gtxe2_channel_001.vp(486): syntax error in protected region.
# 
# ** Error: /home/adrian/opt/Xilinx/Vivado/2017.4/data/secureip/gtxe2_channel/gtxe2_channel_001.vp(486): (vlog-2163) Macro `<protected> is undefined.
# ** Error: /home/adrian/opt/Xilinx/Vivado/2017.4/data/secureip/gtxe2_channel/gtxe2_channel_001.vp(486): (vlog-2163) Macro `<protected> is undefined.
# ** Error: /home/adrian/opt/Xilinx/Vivado/2017.4/data/secureip/gtxe2_channel/gtxe2_channel_001.vp(486): (vlog-2163) Macro `<protected> is undefined.
# ** Error: (vlog-13069) /home/adrian/opt/Xilinx/Vivado/2017.4/data/secureip/gtxe2_channel/gtxe2_channel_001.vp(486): syntax error in protected region.
# 
# ** Error: /home/adrian/opt/Xilinx/Vivado/2017.4/data/secureip/gtxe2_channel/gtxe2_channel_001.vp(486): (vlog-13205) Syntax error found in the scope following '<protected>'. Is there a missing '::'?

Why does it complain about undefined macro?

It looks like Questa can decrypt file, but later fails when trying to parse it.

Maybe it's some obscure Questa bug triggered by Xilinx libraries?

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Xilinx Employee
Xilinx Employee
2,255 Views
Registered: ‎07-16-2008

Re: compile_simlib fails with Questa 10.6b and Vivado 2017.4

Everything looks to be in order from the modelsim.ini. I haven't been able to reproduce the issue in standalone Questa 10.6b in my machine.

Would it be possible to involve Mentor support to look into the vlog failure from Questa tool's perspective? Or perhaps try out 10.6c (but not 10.7 as -novopt is deprecated in the release).

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Adventurer
Adventurer
2,202 Views
Registered: ‎02-06-2012

Re: compile_simlib fails with Questa 10.6b and Vivado 2017.4

I've asked Mentor support to take a look on this, let's see where it goes.
I'll update you if I'll get an answer.
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1,045 Views
Registered: ‎04-01-2019

Re: compile_simlib fails with Questa 10.6b and Vivado 2017.4

Any luck with Mentor support?

I am hitting the exact same issue in "Vivado 2018.2" and "ModelSim - Intel FPGA Edition vlog 10.6d"

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