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sraza
Explorer
Explorer
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Registered: ‎03-13-2012

consecutive command, for write or read, strategy

Dear all,

I have to write VHDL code for DDR3 communication where I have to write code for consecutive WRITE or READ commands...
Now I could not understand of strategy for that...I mean that these commands are feed in to the DDR3 and unless DDR3 is not ready i.e. does not accept the previous command next command should stay in pipeline. Now if lets say 3 or 4 or more commands come in pipeline while the first command is not even accepted at the target side, then how to save these commands, one option I can think of is using buffer, but I could not visualize how to do that in vhdl...

frankly speaking I am not even sure if it is called pipeling or not...
Or is there any better strategy

Please see the figure. 

Any idea, or suggestion...please share

 

 

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Capture.JPG
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3 Replies
bassman59
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Registered: ‎02-25-2008

Usually, there is a FIFO in front of the DDR3 memory interface which buffers up commands, addresses, and data (if a write command). You might think of that as a "pipeline." A state machine manages things by monitoring when the memory is ready for a new command, in addition to other things.

----------------------------Yes, I do this for a living.
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sraza
Explorer
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Registered: ‎03-13-2012

Thank you for reply.

 

Pardon me, but there is confusion on mu side.

 

you said 

 

Usually, there is a FIFO in front of the DDR3 memory interface which buffers up commands, addresses, and data (if a write command). You might think of that as a "pipeline." A state machine manages things by monitoring when the memory is ready for a new command, in addition to other things.

 

Hence you mean that inside the MIG design, there is a FIFO for storing all commands and in the User design for writing or reading consecutive data (where he also has to generate address as well) it is not necessary to include the command FIFO.

 

About the state machine, one machine I know is inside the PHY layer I think, do you mean that?

 

Thanks

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sraza
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Registered: ‎03-13-2012

What I am talking about is explained in the figure:

 

Note that cmd_in is the WRITE or READ command issued by some external module that is responsible for address/command and data transmission.

Whil app_rdy as you might know is the output from the MIG UI indicating ready or not.

while app_cmd, app_en and app_add(not shown here) are the respectives generated in the user design (my design in this case).

 

Hence the following code (just as a beginner code). Can anyone comment 

 

I know that mostly this sort of post where someone share his/her code are ignored but I will really appreciate if someone share his/her experience. please see the figure and code

Note that this is all for MIG deisgn for Virtex-6

timing_diag.JPG

 

--note that my strtegy is to connect command coming from external 
--source to the d_in of FIFO while the cmd_val_in is connect to wr_en
--port of FIFO

process(clk , rst)
begin
if(rst) then
  fetchcmdNadd <= '1';
fifo_rd <= '0'; 
app_addr <= (others => '0');
app_cmd <= (others => '0');
app_en <= '0';
app_end <= '0';
elsif(rising_edge(clk)) then
if(fifoNOTempty = '1' and fetchcmdNadd = '1') then fifo_rd <= '1'; --(connect to rd_en) fetchcmdNadd <= '0'; elsif(app_rdy = '0' and fetchcmdNadd ='0' and fifoNOTempty = '1') then fifo_rd <= '0'; elsif(app_rdy = '1' and fetchcmdNadd ='0' and fifoNOTempty = '1') then fifo_rd <= '1'; end if; --note that fifo width is 32 such that 29 bit address + 3 bit command if(fifo_rd = '1') then app_addr <= dfifo_out(31 downto 3); app_cmd <= dfifo_out(2 downto 0); --cmdin in the figure app_en <= '1'; end if; end if; --end rising edge clk end process;

 

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