cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
Highlighted
Observer
Observer
1,929 Views
Registered: ‎06-21-2017

divider generator 5.1 simulation error

Jump to solution

Hi,

I am trying to simulate the divider generator 5.1 core I have errors in the result. Here is attached the capture image where divider and divisor are selected both to "1". At this point, the output should be 1 but I obtain 0 value and after some clock cycles the output is -65536 and after 917505

I really don´t know how it could be possible. It is due to the latency or a bad testbench simulation?. Do you have any suggestion? Thanks

simulation.png
0 Kudos
1 Solution

Accepted Solutions
Highlighted
Observer
Observer
2,458 Views
Registered: ‎06-21-2017

Do you have any suggestion about it?

Thanks

View solution in original post

0 Kudos
7 Replies
Highlighted
Scholar
Scholar
1,891 Views
Registered: ‎08-01-2012
why not show your code?
0 Kudos
Highlighted
Observer
Observer
1,886 Views
Registered: ‎06-21-2017

here is attached the testbench code

Thanks

0 Kudos
Highlighted
Scholar
Scholar
1,883 Views
Registered: ‎08-01-2012
You havent posted the divider code, and havent shown m_axis_dout_tvalid, which will show when the output is valid. What is the latency of the divider?
0 Kudos
Highlighted
Observer
Observer
1,881 Views
Registered: ‎06-21-2017

Hi,

thank you so much for your response,

The latency was defined as automatic mode with a value of 18. Here is attached the code. Any suggestion will be appreciated

regards

0 Kudos
Highlighted
Observer
Observer
1,875 Views
Registered: ‎06-21-2017

here is also shown the m_axix_dout_tvalid

thanks

 

simulation2.png
0 Kudos
Highlighted
Observer
Observer
2,459 Views
Registered: ‎06-21-2017

Do you have any suggestion about it?

Thanks

View solution in original post

0 Kudos
Highlighted
Scholar
Scholar
1,768 Views
Registered: ‎08-01-2012
Sorry for not replying. Can you post the whole code for div_gen_0, not just the architecture?
0 Kudos