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Explorer
Explorer
4,743 Views
Registered: ‎01-30-2011

doubt in DDS simulation result

 i am designing a cosine wave generator using Xilinx logicore DDS. after that i have simulated using isim 12.3 . but i did not get all output ignals. only get final output. the testbench code is following :

 

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

 

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values

--USE ieee.numeric_std.ALL;

 

ENTITY nw_testcos IS

END nw_testcos;

 

ARCHITECTURE behavior OF nw_testcos IS

 

    -- Component Declaration for the Unit Under Test (UUT)

 

    COMPONENT cosine_wave

    PORT(

         ck : IN  std_logic;

         ck_en : IN  std_logic;

         wave_cosine : OUT  std_logic_vector(7 downto 0)

        );

    END COMPONENT;

   

 

   --Inputs

   signal ck : std_logic ;

   signal ck_en : std_logic ;

 

            --Outputs

   signal wave_cosine : std_logic_vector(7 downto 0);

   -- No clocks detected in port list. Replace <clock> below with

   -- appropriate port name

 

   constant clock_period : time := 50 ns;

 signal stop_the_clock: boolean;

BEGIN

 

            -- Instantiate the Unit Under Test (UUT)

   uut: cosine_wave PORT MAP (

          ck => ck,

          ck_en => ck_en,

          wave_cosine => wave_cosine

        );

 

   -- Clock process definitions

   tb : PROCESS

     BEGIN

 

        ck_en <= '0';

   

    wait for 5 ns;

   ck_en <= '1';

            wait for 15 ns;

    ck_en <= '0';

    wait for 5115 ns;

    ck_en <= '1';

 

    -- Put test bench stimulus code here

    wait for 1 ms;

 

    stop_the_clock <= true;

    wait;

  end process;

 

  clocking: process

  begin

    while not stop_the_clock loop

      ck <= '1', '0' after clock_period / 2;

      wait for clock_period;

    end loop;

    wait;

  end process;

 

please help me........... the output waveform is attched .

cos_wave.JPG
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4 Replies
Moderator
Moderator
4,739 Views
Registered: ‎04-17-2011

Re: doubt in DDS simulation result

When ISIM opens up it would show you only the testbench (top module) signals. Look at the Instances and Process window and click on the small arrow next to testbench, you would see uut under it. Click on uut, and right click, add to wave window would add all you uut signals. You can drill down further in the window and add the signals you are interested in.

Alternately use TCL command "wave add" to add the signals or module you are interested in to wave window. For details on wave add refer to chapter 10 of ISIM user guide.
Regards,
Debraj
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Explorer
Explorer
4,730 Views
Registered: ‎01-30-2011

Re: doubt in DDS simulation result

sir , ihave done it as your previous post . ihave attched the snapshot below . but i don't catch the output of 360 degree angles ,such as cos1 = 0 ,cos 60 = 0.5 , etc . how will i get it .  ihave searched sine-cos lookup table in logicore . but it is not available .then hoe will i proceed . i have taken the DDS logicore block from wavesynthesis . will i have to access it from logicore  trig function ? plz help.

wave.JPG
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Explorer
Explorer
4,718 Views
Registered: ‎01-30-2011

Re: doubt in DDS simulation result

aplease anybody clear my doubt..............

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Moderator
Moderator
4,711 Views
Registered: ‎04-17-2011

Re: doubt in DDS simulation result

Can you look in the core's functional model and look for the signal you are interested in. Select the core in Project Navigator and in the window below it double click on View Functional Model. Once you find it in the code, look for it the instance and hierarchy tab in ISIM and add it to the waveform window. Sorry, I have never simulated this core so no idea where your signal would be :)
Regards,
Debraj
----------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful and reply oriented.
----------------------------------------------------------------------------------------------
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