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Explorer
Explorer
346 Views
Registered: ‎12-05-2016

error in simulation : [VRFC 10-704] formal uart_rx has no actual or default value

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Hi all,

I got the attached error while doing simulation. When I checked UART_RX is a top level input and it is correctly port mapped to an internal module. then why the tool is throwing this error? 

port map section

--------------------------------

uart : UART_Wrapper
Port map (clk_uart => clkToUart,-- 10MHz
tx_out => UART_TX,
rx_in => UART_RX,
--- reset => gt0_tx_system_reset_c,
rd_cnt => fifo_rd_cnt,
wr_cnt => fifo_wr_cnt,
fifo_data => fifo_data1,
fifo_read => fifo_rd_en,
tx_clk => gt0_txusrclk2_i);

------------------------------------------------

I was able to generate the bit file. 

Any help is appreciated. 

 

no_formal.JPG
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Xilinx Employee
Xilinx Employee
317 Views
Registered: ‎07-16-2008

If it passes in synthesis, did you drive it in testbench if this is a top level input port?

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Xilinx Employee
Xilinx Employee
318 Views
Registered: ‎07-16-2008

If it passes in synthesis, did you drive it in testbench if this is a top level input port?

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Explorer
Explorer
284 Views
Registered: ‎12-05-2016
Exactly. I missed it in the test bench. I was looking at only design sources.
Thank you.
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