06-25-2019 09:39 AM
If the FPGA transmits X bits of data per clock cycle, and the FPGA is running at a frequency F, then the throughput is X * F bits per second. To increase the throughput you can increase X, or F, or both.
06-25-2019 09:50 AM
thanks sir for your reply,so what i understand ,for exemple the frequency is 120mhz i i have totals bits is 216450 pixel and i send line by line and in each line i send in 1ns and each line is in 16 bits so : 120 * 16 ?
06-25-2019 09:58 AM
As I tell my students: go wide.
A 512 bit wide bus at 100 MHz is 51.2 Gb/s. A 1024 bit wide bus at 100 MHz is 100 Gb/s. A 4,096 wide bus at 200 MHz is 800 Gb/s.
Now getting that in or out of the device is the next challenge, but depending on how many gigabit transceivers you have, that can be in the hundreds of Gb/s, too.