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Highlighted
590 Views
Registered: ‎05-10-2020

hello i have a problem in the test bunch in get no module file

im using vivado 2017.2

this is the program

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity dec is
Port (bcd:in std_logic_vector(3 downto 0);
segment : out std_logic_vector(6 downto 0) );
end dec;

architecture Behavioral of dec is

begin
process(bcd)
begin
case bcd is
when "0000"=>segment<="1111110";
when "0001"=>segment<="0110000";
when "0010"=>segment<="1101101";
when "0011"=>segment<="1111001";
when "0100"=>segment<="1001100";
when "0101"=>segment<="1011011";
when "0110"=>segment<="1011111";
when "0111"=>segment<="0001111";
when "1000"=>segment<="1111111";
when "1001"=>segment<="0000100";
when others=>segment<="0110111";
end case;
end process;

end Behavioral;

**** test bunch

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity testd is
Port ( );
end testd;

architecture Behavioral of testd is
component dec port
(bcd:in std_logic_vector(3 downto 0);
segment : out std_logic_vector(6 downto 0)
);
end component;

signal bcd: std_logic_vector(3 downto 0);
signal segment : out std_logic_vector(6 downto 0);

begin
uut: dec port map( bcd=> bcd, segment => segment);
stimulus: process
begin
bcd<="0001";
wait for 100 ns;
bcd<="0010";
wait for 100 ns;
bcd<="0011";
wait for 100 ns;
bcd<="0100";
wait for 100 ns;
bcd<="0101";
wait for 100 ns;
bcd<="0110";
wait for 100 ns;
bcd<="0111";
wait for 100 ns;
bcd<="1000";
wait for 100 ns;
bcd<="1001";
wait ;
end process;
end Behavioral;

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10 Replies
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Voyager
Voyager
578 Views
Registered: ‎06-20-2012

Which problem ?

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0 Kudos
559 Views
Registered: ‎05-10-2020

Problem in the simulation in the bench test
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Highlighted
Voyager
Voyager
556 Views
Registered: ‎06-20-2012

Again which problem !!!!

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Highlighted
553 Views
Registered: ‎05-10-2020

Yes
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Highlighted
553 Views
Registered: ‎05-10-2020

No module file
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Voyager
Voyager
544 Views
Registered: ‎06-20-2012

Post at least the simulator output

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Highlighted
538 Views
Registered: ‎05-10-2020

No module file always the same problem
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Highlighted
Voyager
Voyager
523 Views
Registered: ‎06-20-2012

On the testbench remove

Port ( );

remove out

signal segment : out std_logic_vector(6 downto 0);

Please check the simulator outputs.

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Highlighted
516 Views
Registered: ‎05-10-2020

I remove it and it still the same problem
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Voyager
Voyager
515 Views
Registered: ‎06-20-2012

share a screenshot

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