11-23-2020 08:12 AM
I am trying to put together a hierarchical design made up of two modules. A pulse width detector and a bit decoder. I have independently simulated both of these modules and they work. I am trying to put this together in a top level design and simulate it next. The pulse width detector works with my simulation in the top level design, but I keep getting Undefines for most of my signals in the bit detector.
Could anyone please help me figure out my issues? My files are attached.
11-23-2020 08:16 AM
The o_num_bits is the name of a port at PW_Counter_Top and it is also defined as a signal in your wrapper top-level. Use another signal name and it would work.
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11-23-2020 08:47 AM
Re-using a component port name as a local signal is fine.
@ejleiss The problem is in "Top_wrapper", there is a signal called o_num_bits. It is only connected to the input of bit_decoder "i_num_bits", hence will always be "UUUU". The "o_num_bits" in the "PW_counter_TOP" is connected to PW_out.
11-23-2020 08:57 AM
Thank you both for your responses. So I am obviously not understanding something... o_num_bits is the output of PW_Counter_Top and is supposed to be fed into i_num_bits of the Bit_Decoder module. I thought I was doing that in the Top_Wrapper by setting i_num_bits <= o_num_bits in the port mapping of Bit decoder...
Port mapping o_num_bits to PW_out was just for diagnostic purposes. How would I pass o_num_bits to i_num_bits properly?