11-06-2012 11:43 PM
I want to trace one datapath by chipscope in my design, but after sysnthesize, I found some of reg signals are disappear. As other peoples said, I Keep hierarchy YES, and add the constraint for the the reg signal I want to see (*keep = "TRUE"*)
But it seems no affect. Still cann't see this signal. Could somebody give me some suggestions?
11-07-2012 10:14 AM
Sometimes a signal is still in the design, but has been renamed. Remember that in a heirarchical
design, any net that goes through a module port may have different names at each level of the
hierarchy, and at the end only one of these names remains. For XST this is normally the name
of the reg where the signal is driven. So let's say you have a top level module that instantiates
a lower level module like
. . .
and my_lower_module has a port defined as:
output wire [7:0] d_out,
and within the module:
reg [7:0] data_within_mlm;
assign d_out = data_within_mlm;
Now you have an 8 bit bus that could be called:
I think in this case you'll see the last one, but it's up to XST to decide. So you need to
search for any of these in the ChipScope inserter.
11-07-2012 04:32 PM
In the case that the concerned reg signals are unconnected (sourceless or loadless), "keep" property doesn't prevent trimming. You need to apply "S" (Save Net Flag).