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4,262 Views
Registered: ‎11-13-2009

how to simulate top-level designs with custom created NGC files

Hi all,

 

I've scoured the internet for a solution to this problem and have yet to come up with anything concrete.  I hope someone can help!

 

I have a multi-level design that I wish to simulate.  The design consists of a top-level design which instantiates several lower level design in the form of synthesized .ngc files.  I have created each .ngc file one by one (aka I have the source vhdl  to them).  When I go to modelsim the top-level the design the NGC files are not seen by modelsim (obviously).  So, I tried wrapping the ngc's similar to how Xilinx does their coregen parts and I haven't had any luck.

 

Basically my question is, how do I use the modelsim compiled files from the lower-level projects in a higher-level design?  Is there a way to export the compiled files into a library that can then be later imported by another design?

 

I've also included my attempt at generating a wrapper VHDL file for modelsim to use.  This is template code only.  I just followed the layout that Xilinx uses for their coregen parts.  The []'s are not in the src vhdl (obv).

 

Thanks!

- Joseph

 

P.S.  Feel free to ask for clarification is any is needed.

 

 

*** CODE SNIPPET ***

 

 

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
library CEDALib;
-- synthesis translate_on
ENTITY [NGC_FILE_NAME] IS
PORT (
    [PORT1] : in [VHDL_TYPE];
    [PORT2] : in [VHDL_TYPE];
    [PORT3] : out [VHDL_TYPE]
);
END [NGC_FILE_NAME];
ARCHITECTURE [NGC_FILE_NAME]_a OF [NGC_FILE_NAME] IS
-- synthesis translate_off
component wrapped_[NGC_FILE_NAME]
port (
    [PORT1] : in [VHDL_TYPE];
    [PORT2] : in [VHDL_TYPE];
    [PORT3] : out [VHDL_TYPE]
);
end component;
-- Configuration specification 
    for all : wrapped_[NGC_FILE_NAME] use entity CEDALib.[NGC_FILE_NAME](behavioral)
    --generic map();
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_[NGC_FILE_NAME]
        port map (
            [PORT1] => [PORT1],
            [PORT2] => [PORT2],
            [PORT3] => [PORT3]
        );
-- synthesis translate_on
END [NGC_FILE_NAME]_a;

 

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

-- synthesis translate_off

library CoreLib;  -- custom library ??

-- synthesis translate_on

ENTITY [NGC_FILE_NAME] IS

PORT (

   [PORT1] : in [VHDL_TYPE];

   [PORT2] : in [VHDL_TYPE];

   [PORT3] : out [VHDL_TYPE]);

END [NGC_FILE_NAME];

ARCHITECTURE [NGC_FILE_NAME]_a OF [NGC_FILE_NAME] IS

-- synthesis translate_off

component wrapped_[NGC_FILE_NAME]

port (

    [PORT1] : in [VHDL_TYPE];

    [PORT2] : in [VHDL_TYPE];

    [PORT3] : out [VHDL_TYPE]);

end component;
-- Configuration specification

     for all : wrapped_[NGC_FILE_NAME] use entity CEDALib.[NGC_FILE_NAME](behavioral);

-- synthesis translate_on

BEGIN

-- synthesis translate_off

inst: wrapped_[NGC_FILE_NAME]

        port map (

            [PORT1] => [PORT1],

            [PORT2] => [PORT2],

            [PORT3] => [PORT3] 

       );

-- synthesis translate_on

END [NGC_FILE_NAME]_a;

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1 Reply
ywu
Xilinx Employee
Xilinx Employee
4,247 Views
Registered: ‎11-28-2007

You can use "netgen" to generate simulation models from the ngc files (see the snapshot below). Please take a look at the "Command Line Tools User Guide" (http://www.xilinx.com/support/documentation/sw_manuals/xilinx11/devref.pdf) for more details.

 

 

Cheers,
Jim
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