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mohatif
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Registered: ‎12-16-2010

master thesis

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I'm finalizing my master degree, but i have problem in analytical analysis of my design.. i mean i design a hardware design on xc4vfx12 and i got from simulation very good results.. but i need to make analytical study that may follow the simulation results for maximan freq. so i think that i will get my schematic design and i will convert it into AND, OR, XOR ,etc. Then, i have to get their timing in (ns) according to xc4vfx12  which i don't have and i need link for it. Then, i will get path from i/p and output and count averall ns. then reverse it. Any help from you ..any enhancement for my idea?

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edv
Xilinx Employee
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Registered: ‎08-15-2007

You can use an STA tool such as Xilinx Timing Analyzer (TRCE) to do the maximum frequency analysis for you.  You can apply a timing constraint on the design via a UCF PERIOD constraint and then run the tool.  It will report whether you have a positive of negative slack on the desired period.  From here you'll determine the fastest speed the design can run at.

 

Check out the following videos which can get you started with how to use constraints on the design:

 

http://www.youtube.com/watch?v=dRM0HVdqvZo

http://www.youtube.com/watch?v=38Px7CmGczo

http://www.youtube.com/watch?v=P3rQssXEFm8

 

For more details, check out the Timing Constraints User Guide (http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_3/ug612.pdf)

 

Hope this helps.

Eddie

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edv
Xilinx Employee
Xilinx Employee
11,943 Views
Registered: ‎08-15-2007

You can use an STA tool such as Xilinx Timing Analyzer (TRCE) to do the maximum frequency analysis for you.  You can apply a timing constraint on the design via a UCF PERIOD constraint and then run the tool.  It will report whether you have a positive of negative slack on the desired period.  From here you'll determine the fastest speed the design can run at.

 

Check out the following videos which can get you started with how to use constraints on the design:

 

http://www.youtube.com/watch?v=dRM0HVdqvZo

http://www.youtube.com/watch?v=38Px7CmGczo

http://www.youtube.com/watch?v=P3rQssXEFm8

 

For more details, check out the Timing Constraints User Guide (http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_3/ug612.pdf)

 

Hope this helps.

Eddie

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mohatif
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Registered: ‎12-16-2010

thank you for your replay

i think these material are used to understand how xilinx counting clock, but i need to be away from xilinx tools and count clock cycle in analytical way using only specs of gates delay in xc4vfx12

or

may be i didn't get your idea?

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bassman59
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Registered: ‎02-25-2008

 


@mohatif wrote:

thank you for your replay

i think these material are used to understand how xilinx counting clock, but i need to be away from xilinx tools and count clock cycle in analytical way using only specs of gates delay in xc4vfx12

or

may be i didn't get your idea?


What kind of silly master's thesis topic is this?

 

----------------------------Yes, I do this for a living.
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mohatif
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lol man! it isn't depend on topic .. it's some kind of verification to your work .. i mean we have alot of lows that are model somethings in real life like acceleration = velocity over time this low is accepted as analytical counting is approximately equal real life cases
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awillen
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Registered: ‎11-29-2007

 


@mohatif wrote:
lol man! it isn't depend on topic .. it's some kind of verification to your work .. i mean we have alot of lows that are model somethings in real life like acceleration = velocity over time this low is accepted as analytical counting is approximately equal real life cases

 

Sorry to say it, but your post is close to incomprehensible. I'll try to reword it:

You want to do an empirical study to test the timing report of the Xilinx tools, just like theories in natural sciences are tested by empirical experiments.

Is that about correct?

 

 


 

i think these material are used to understand how xilinx counting clock, but i need to be away from xilinx tools and count clock cycle in analytical way using only specs of gates delay in xc4vfx12

 


 

"count clock cycle" – what do you mean by that? Do you want to determine the minimum period of a clock so that the design still works?

 

 

From your posts it seems that you're not very adept in the internals of FPGAs. For example, FPGAs are not built from "gates" (actually, not even ASICs are built from gates, but from standard cells). I strongly suggest that you explain exactly what it is that you want to do in your Master's thesis, before you start a topic that doesn't make sense. We're here to help you, and if you let us help you, then we might prevent you from making a big mistake.

 

 

Adrian



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mohatif
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thx you for your replying friend. I will explain for you exactly what i want to do.

 

I made enhancements on certain a RSA implementation on FPGA for different precision 32,64, ..etc. I can finish my thesis till this point, but if Supervisor suggest to make analytical study and show if simulation result follow analytical study. How can i count maximam freq. analytically?

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awillen
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Registered: ‎11-29-2007

Please clarify the following points:

  1. "make analytical study" – does that mean that you download the design to an FPGA and run it?
  2. "show if simulation result follow analytical study" – what does that mean? Do you want to check whether the simulation you perform on a computer returns the same results as the design running on an actual FPGA?
  3. "count maximam freq. analytically" – do you want to determine the maximum clock frequency of the design running on an actual FPGA?

I think I understand what you're trying to do, but please answer these points, just to be clear.

 

 

Adrian



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mohatif
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Answers of your questions are the following:

 make analytical study means:  if my design has AND 2 X 1, with precision 32 bits. suppose OR/AND gates with 32 bits i/o has delay  = 16 X OR/AND gate delay with 2 bit i/o

 

     Delay(OR/AND(32)) =  16 * Delay(OR/AND(2))

     if Delay(OR/AND(2)) = 5ns then Delay(OR/AND(32)) = 16*5 ns

 

Previous equations are considered as analytical study. Xilinx simulation may support these equations or not if simulation supports theses equations then your work is somehow right.

 

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awillen
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What you're planning to do does not make sense, for the following reasons:

  1. As I mentioned before, FPGAs are not built up from AND/OR/etc. gates. If you want to know how, e.g., the Virtex-5 looks inside, then read the Virtex-5 FPGA User Guide.
  2. Your calculations do not seem to take into account the network ("routing") delay, which has a considerable impact and can easily surpass the logic delay. If you ignore the network delay, then your results are useless garbage.
  3. The architecture and the logic delays within a slice are well documented, but you won't find any details about the routing architecture and delays. And even if there were, you'd have to manually trace all routes in PlanAhead, which is infeasible for even medium-sized designs.
  4. In the hypothetical case that you had all necessary information, traced all routes, made no mistakes, then you'd arrive at the exact same results as the post PAR static timing analysis of the ISE tools. Because that's what they do: they take the most accurate information available and apply it to your design in order to determine the minimum clock period required.

So you see, what you're trying to do is not only not possible, it would even be redundant and pointless if it weren't imossible.

 

 

Adrian



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mohatif
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so according to my explaination what do you think the best way to analysis design?

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awillen
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Registered: ‎11-29-2007

Create timing constraints for your clock. Then set the PAR process properties to "Performance evaluation" and implement your design. The report will tell you the maximum clock frequency.

 

Note: don't rely on the synthesis report, as it will give you only very coarse timing values.

 

 

Adrian



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mohatif
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Man .. i found what i'm searching for ... you can read what i'm writing and you will got it....

there is common analysis called equivelant gate delay which is abstract and independant from any specified hardware to analysis your design

http://en.wikipedia.org/wiki/Gate_equivalent

http://www.seas.upenn.edu/~ese201/lab/CarryLookAhead/CarryLookAheadF01.html

 

it's supposed that simulation results for specific hardware of FBGA are near to this abstract

 

understood


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mohatif
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i want to mentian that before xilinx has parameter called equivelant gates(that i was mentioned in last post), but recent versions doesn't have this parameter.

i hope it give you good over view about what i was search for.

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awillen
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Registered: ‎11-29-2007

Equivalent gates?

I've got to tell you: if that's actually what you were looking for, then your problem description skills are really, really, lousy. I mean, how do you get from "equivalent gates" to "simulation", "maximum frequency", "delay", etc.?



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eilert
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Registered: ‎08-14-2007

Hi,

when you are trying to work with gate equivalents on FPGA technologies, you completely lost your track.

You can search comp.lang.fpga for detailed discussions why this method just not works for FPGAs and FPGA designs.

And these discussions are mainly focussed on the area aspect. Using that approach for timing is even worse.

 

In short:

Besides the fact that the main cause for delays in sub micron technologies is the routing, FPGAs consit of LUTs instead of gates, And it depends on your design how much logic can be absorbed into one LUT. So a simple inverter can have the same logic delay as a complex (up to) four (or six) input function (e.g. half adder or two input mux).

 

And the CLA example makes it even funnier.

This analysis works on ASIC technologies. FPGAs have special hardware support for carry chains. So in reality a large ripple adder in an FPGA is still faster than a CLA architecture that uses just LUTs. There may be a turning point at very high bit numbers, but that point is far beyond the results you would get from a unit delay analysis as you intend to do.

 

Also, you should read the wikipedia article more carefully.

It just talks about standard cell technology, drive strength and transistors. Nothing about timing is mentioned.

This aproach is intended for area scaling on the transistor level in comparable(!)  technologies.

 

Have a nice synthesis

  Eilert

 

mohatif
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Registered: ‎12-16-2010

I forgot important thing that i'm talking to technology contributer.. not researchers ... but i will give you a conclusion

when you are researching you should first analysis your idea on paper by hand .. then simulate or implement what ever you want.. i hope you got message man

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