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aleluca
Newbie
Newbie
877 Views
Registered: ‎04-18-2018

modelsim vivado include file .vh

Hello,

my enviroment is based on

modelsim 10.5c

Vivado 2016.2

I'm checking the testing library for the project based on ome ip generated by vivado, in particular I'm facing some problem to import the simulation environment for the DDR4 behavior test bench.

A this moment I've a problem to import the complete bus for the

u_ddr_iob

defined in

 ..\ddr4sdram\ip_0\rtl|phyddr4sdram_phy_ddr4.sv

because in the bus declaration is placed the following:

/ddr4_phy_v2_0_1_iob # (
    .BYTES          (BYTES)
   ,.IOBTYPE        (IOBTYPE)
   ,.DRAM_TYPE      (DRAM_TYPE)
   ,.DQS_BIAS       (DQS_BIAS)
   ,.BANK_TYPE      (BANK_TYPE)
   ,.USE_DYNAMIC_DCI(USE_DYNAMIC_DCI)
) u_ddr_iob (
    .phy2iob_q_out_byte   (phy2iob_q_out_byte)
   ,.phy2iob_odt_out_byte (phy2iob_odt_out_byte)
   ,.phy2iob_t            (phy2iob_t)
   ,.iob2phy_d_in_byte    (iob2phy_d_in_byte)
   // spyglass disable_block WRN_32
   `include "ddr4sdram_phy_iobMapDDR4.vh"
   // spyglass enable_block WRN_32
);

 

The vh file (ddr4sdram_phy_iobMapDDR4.vh) report as follows

 

,.mcal_rd_vref_value (

{

 

    mcal_rd_vref_value[27:21],

    mcal_rd_vref_value[20:14],

    mcal_rd_vref_value[13:7],

    mcal_rd_vref_value[6:0],

    7'b0,

    7'b0

}

)

 

,.iob_pin (

{

ddr4_nc[0],

ddr4_dq[31],

ddr4_dq[30],

                               ….

ddr4_adr[0]

}

)

 

But Modelsim reports:

# ** Error: ../src/ddr4_test.srcs/sources_1/ip/ddr4sdram/ip_0/rtl/map/ddr4sdram_phy_iobMapDDR4.vh(2): near ",": syntax error, unexpected ',', expecting class

 

My Modelsim is a full licensed   and works fine with mixed language project. How can I overcame to this issue?

thanks in advance for your support.

Best regards,

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1 Reply
amaccre
Moderator
Moderator
842 Views
Registered: ‎04-24-2013

Duplicate of the following thread:

 

https://forums.xilinx.com/t5/Simulation-and-Verification/modelsim-include-directory-vh-file/td-p/848961

 

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