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jw_l3harris
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Registered: ‎12-09-2019

ncvhdl_p: *E,MULVLG Error when trying to simulate native FIFO

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I am receiving the following error in NCSIM when compiling a VHDL testbench that includes a FIFO IP source, which is the unencrypted Verilog file in the IP simulation dir. Opening the verilog file I only see one module. Not sure where it is seeing two of them from. I am including the unisims, unimacro, and glbl libraries in my irun command per AR# 56713.

ncvhdl_p: *E,MULVLG (..//tb/tb_rx25g_neo.vhd,392|35): Multiple Options for Binding Specified Verilog Unit (worklib.fifo_async_22x32_dist):
worklib.fifo_async_22x32_dist:module
worklib.fifo_async_22x32_dist:v

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graces
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Registered: ‎07-16-2008

What source files did you compile for the FIFO IP?

I'd suggest that you run export_simulation Tcl command for the IP in Vivado. This will export a simulation script based on the target simulator specified. You can then integrate the compile/elaborate commands to your custom script.

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graces
Moderator
Moderator
556 Views
Registered: ‎07-16-2008

What source files did you compile for the FIFO IP?

I'd suggest that you run export_simulation Tcl command for the IP in Vivado. This will export a simulation script based on the target simulator specified. You can then integrate the compile/elaborate commands to your custom script.

-----------------------------------------------------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
If starting with Versal take a look at our Versal Design Process Hub and our Versal Blogs.
-----------------------------------------------------------------------------------------------------------------------

View solution in original post

jw_l3harris
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Observer
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Registered: ‎12-09-2019

Thanks, generated the scripts as you suggested, I will look through them.

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jw_l3harris
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Registered: ‎12-09-2019
Able to get working using by viewing the generated scripts from the export_simulation command and updating my bash script. Thanks.
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