cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
Highlighted
Scholar
Scholar
5,637 Views
Registered: ‎04-26-2012

no VHDL simulation models for XPM's ?

According to UG974, UNIMACRO's are not supported in Ultrascale and have been replaced[1] by XPM's

 

But there do not appear[2] to be any VHDL simulation models available for these XPM macros in 2017.3, making it impossible to do functional simulation of XPM's within a VHDL simulation environment[3].

 

The problems this creates are clearly summarized in this 2015 thread (unanswered) regarding the similar situation of missing VHDL simulation support in Vivado for the SIMPRIM library:

  https://forums.xilinx.com/t5/Simulation-and-Verification/Post-Implementation-Timing-Simulation-not-supported-for-VHDL/m-p/650041

 

Q1) Have I overlooked any VHDL XPM simulation models to be found somewhere else in the Vivado libraries?

Q2) If not, does Xilinx plan to support VHDL simulation for the XPM's in a future release?

 

-Brian

 

[1] 

XPM1.png

[2] Searched UG900, UG895, UG974, UG1118 without finding any references to VHDL XPM simulation models

     Searched the 2017.3 Xilinx install directories:

     ./data/ip/xpm has only SystemVerilog implementations, the only VHDL is just the component declarations found in xpm_VCOMP.vhd

 

[3] Unless one has a mixed language simulator with SystemVerilog support.

     Post-synthesis netlist simulation is not a viable answer.

22 Replies
Highlighted
Moderator
Moderator
5,615 Views
Registered: ‎04-24-2013

Hi @brimdavis,

 

Starting in 2015.3, any IP that was delivered with both VHDL and Verilog files for simulation began to deliver Verilog only.

This was to ensure no functional conflict when locked and new IP were mixed in a design.
 
User Guide 900 has the following information on running post synthesis and implementation functional and timing simulation in 3'rd party Simulators.
 
Capture1.PNG
 
Capture2.PNG
 
Let me know if this helps.

Best Regards
Aidan
 
 
------------------------------------------------------------------------------------------------------------------
Please mark the Answer as "Accept as solution" if this answered your question
Give Kudos to a post which you think is helpful and may help other users
------------------------------------------------------------------------------------------------------------------
 
 

------------------------------------------------------------------------------------------------------------------
Please mark the Answer as "Accept as solution" if this answered your question
Give Kudos to a post which you think is helpful and may help other users
------------------------------------------------------------------------------------------------------------------
0 Kudos
Highlighted
Scholar
Scholar
5,606 Views
Registered: ‎04-26-2012

@amaccre "Let me know if this helps."

 

Not even close- I am not asking about Verilog IP delivery.

 

I am asking about the complete lack of a VHDL simulation ***library*** for these new XPM macros.

 

This is a major regression from the UNIMACRO's they are supposed to replace, which provided both VHDL and Verilog simulation models.

 

>

> User Guide 900 has the following information on running post synthesis and implementation functional and timing simulation 

>

Did you actually read my original post, or just skim it? With highlighting:

  "

  " [3] Unless one has a mixed language simulator with SystemVerilog support.

  "     Post-synthesis netlist simulation is not a viable answer.

  "

 

EDIT:  I pointed to that 2015 thread about the SIMPRIM library because it summarized the various user issues that arise from Xilinx's failure to provide VHDL versions of their simulation libraries, to wit:

 

 1) Some users have qualified simulation flows that are VHDL only.

      "Many of us have corporate standards that dictate the use of VHDL."

 

 2) Mixed mode simulators cost much more

       "such as QuestaSim.  The cost of a Mixed-Language license is on the order of $50K versus a VHDL-only license for $25K.  "

 

-Brian

Highlighted
Xilinx Employee
Xilinx Employee
5,581 Views
Registered: ‎07-16-2008

The behavioral models for XPM are in single language (system verilog). They're located at:

$XILINX_VIVADO/data/ip/xpm/xpm_cdc(fifo, memory)/hdl

-------------------------------------------------------------------------
Don't forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------
0 Kudos
Highlighted
Scholar
Scholar
5,566 Views
Registered: ‎04-26-2012

@graces "The behavioral models for XPM are in single language (system verilog). They're located at:

$XILINX_VIVADO/data/ip/xpm/xpm_cdc(fifo, memory)/hdl"

 

Again, why can't Xilinx support personnel actually read my original message before just repeating what I already wrote?

 

From my original post:

"

" Searched the 2017.3 Xilinx install directories:

"    ./data/ip/xpm has only SystemVerilog implementations, the only VHDL is just the component declarations

"    found in xpm_VCOMP.vhd

"

" Q1) Have I overlooked any VHDL XPM simulation models to be found somewhere else in the Vivado libraries?

" Q2) If not, does Xilinx plan to support VHDL simulation for the XPM's in a future release?

"

 

Please file a CR against this issue, as it is completely unacceptable that a ***DEVICE LIBRARY*** is available only for Verilog simulation.

 

Users do DESIGN ENTRY with UNISIM/UNIMACRO and now XPM libraries, which need to be available in both VHDL and Verilog as they have been for years- as I said in my original post, post-synthesis functional simulation is NOT an 'answer' to this Vivado regression.

 

-Brian

 

Highlighted
Xilinx Employee
Xilinx Employee
5,526 Views
Registered: ‎07-16-2008

There's no plan to support VHDL model for XPM in future releases.

-------------------------------------------------------------------------
Don't forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------
0 Kudos
Highlighted
Scholar
Scholar
5,515 Views
Registered: ‎04-26-2012

@graces "There's no plan to support VHDL model for XPM in future releases."

 

Again:

 

Please file a CR against this issue, as it is completely unacceptable that a ***DEVICE LIBRARY*** is available only for Verilog simulation.

 

Users do DESIGN ENTRY with UNISIM/UNIMACRO and now XPM libraries, which need to be available in both VHDL and Verilog as they have been for years- as I said in my original post, post-synthesis functional simulation is NOT an 'answer' to this Vivado regression

 

 
EDIT: Summary of justifications for filing a CR
 1) The absence of XPM VHDL simulation models is a regression from the UNIMACRO library they replace.
 2) Post-synthesis functional simulation is not a viable substitute for simulation associated with design entry.
 3) Some users have qualified simulation flows that are VHDL only.
 4) Mixed-language simulator licenses cost more than single-language.
 5) FPGA Design Language Usage numbers, 2016 WRG Study :
     VHDL: 62%  Verilog: 55%   SystemVerilog: 21%   C/C++: 16%   SystemC: 5%
    ( inclusive, hence the sum > 100% )

Highlighted
Adventurer
Adventurer
5,432 Views
Registered: ‎02-06-2012

I support this request. VHDL library is essential for many companies and projects.

PLEASE FILE A CR AGAINST THIS ISSUE.
Highlighted
Scholar
Scholar
5,416 Views
Registered: ‎08-24-2011

I fully agree. Possibility to simulate the design in pure VHDL is often essential im my project!

With best regards,

WZab

Highlighted
Xilinx Employee
Xilinx Employee
5,400 Views
Registered: ‎07-16-2008

The Xilinx direction for any new development is in Verilog. It can be overridden with business justification though.

If you have a strong demand, I'd suggest that you open a Service Request with Technical Support and get a CR filed. The SR will be linked to the CR. If quite a few SRs are linked to the CR, the chance to get it implemented will be larger.

-------------------------------------------------------------------------
Don't forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------
0 Kudos
Highlighted
Scholar
Scholar
3,944 Views
Registered: ‎04-26-2012

@graces   "If you have a strong demand, I'd suggest that you open a Service Request with Technical Support and get a CR filed. "


 Like many Xilinx customers, my account lost WebCase (ne SR) ability after the Great Xilinx Customer Support Purge of 2013 [1].

 My only 'Technical Support' is to post here on the forums and request that a CR be filed.

 So, for the third time:
   Please file a CR against this XPM library issue.   See my post of 12-07-2017 for a list of justifications.

 

   If you are unable to file a CR, then please escalate this request to someone who can.

>
> The Xilinx direction for any new development is in Verilog. It can be overridden with business justification though.

> <snip>  If quite a few SRs are linked to the CR, the chance to get it implemented will be larger.

>
 Given that a majority of FPGA design starts are still in VHDL, the availability of component libraries for VHDL simulation should be a fundamental engineering requirement for Vivado.

 If Xilinx is treating this as a value-driven marketing decision, with the only input being from an opaque CR/SR process with no visibility to the majority of Xilinx customers, then Xilinx's engineering processes are fundamentally broken.

-Brian

[1] Shortly after Vivado launch, Xilinx ended Webcase Support for many customers:
    https://forums.xilinx.com/t5/Welcome-Join/WebCase-support-no-longer-available-to-some-users/td-p/329925

 

 

Highlighted
Xilinx Employee
Xilinx Employee
3,933 Views
Registered: ‎07-16-2008

Brian,

 

The SR process is how a customer sourced CR is formally filed. You may contact your distributed FAE to create an SR.

 

I filed an enhancement CR-991610 against XPM and passed on your comments. 

-------------------------------------------------------------------------
Don't forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------
Highlighted
Scholar
Scholar
3,922 Views
Registered: ‎08-01-2012

Can you provide a use case where mixed mode is not possible?

Most simulators support mixed mode now - even the free version of modelsim you get from Altera/Intel (since 2015).

0 Kudos
Highlighted
Scholar
Scholar
3,914 Views
Registered: ‎04-26-2012

@richardhead "Can you provide a use case where mixed mode is not possible?"

 

The availability of mixed mode simulators does not excuse Xilinx from providing single-language simulation libraries.

 

I typically use GHDL for IP development.

 

And from earlier in the thread:

"

" EDIT:  I pointed to that 2015 thread about the SIMPRIM library because it summarized the various user issues that arise

" from  Xilinx's failure to provide VHDL versions of their simulation libraries, to wit:

"

" 1) Some users have qualified simulation flows that are VHDL only.

"      "Many of us have corporate standards that dictate the use of VHDL."

"

" 2) Mixed mode simulators cost much more

"       "such as QuestaSim.  The cost of a Mixed-Language license is on the order of $50K versus a VHDL-only license for $25K.  "

-Brian

Highlighted
Adventurer
Adventurer
1,925 Views
Registered: ‎04-22-2008

Xilinx --

Is this still the official statement on the matter?  Are the XPM simulation models just going to be SystemVerilog only, and if VHDL users don't like it they can find a different vendor?

 

Highlighted
Teacher
Teacher
1,918 Views
Registered: ‎07-09-2009

I'd imagine, like most companies, Xilinx care for the bottom line
the big guys make the money for them,
big guys have mixed mode simulators,

I work for both big and small companies,
the extra cost of a modelsim / questa for multiple languages is a significant overhead for the small specialist guys,

The xilxin sim offering is better, but still not as good as the comercial products,

It was a big loss to the world when Xilinx without pre announcement dropped VHDL support to the lowest they could manage.

Now if they had decided to only support VHDL, then they could use automatic tools to make the Verilog, but in my opinion, being a US company, the advantages of VHDL , although originally being a US mill product, is lost.

As to why XPM are in System verilog, is even more of an amazement, XPM are relatively small, so should not be to difficult for them to make a VHDL version.
<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
Highlighted
Adventurer
Adventurer
1,908 Views
Registered: ‎04-22-2008

I even HAVE a mixed-mode simulation license.  But the XPM models have been constructed around the superfluous need for a GLBL Verilog file.  Which I managed to hunt down and compile into my library as well.  But now I can't just simulate my testbenches, I have to call vsim with both glbl AND my testbench as co-top-level entities, which means that I can't simply click on one of my benches in the Modelsim Library browser and hit Simulate.

It's just one unnecessary hoop to jump through after another.

Highlighted
Scholar
Scholar
1,898 Views
Registered: ‎04-26-2012

@rgaddi   "But the XPM models have been constructed around the superfluous need for a GLBL Verilog file."

When I last looked into this (2018.2), it appeared that you could bypass the need for glbl.v [ EDIT(correction): this doesn't work, see following posts ] by adding defining a  `define ONESPIN  to the XPM sources (which turns off the XPM GSR stuff for a formal verification flow); see my and richard's posts on this thread:

https://forums.xilinx.com/t5/Simulation-and-Verification/Simulating-XPM-FIFO-in-ActiveHDL-Error-with-2018-2-libraries/m-p/883224

-Brian

Highlighted
Scholar
Scholar
1,884 Views
Registered: ‎08-01-2012

@brimdavis 

This just doesnt work (I tried). Stuff just doesnt initialise properly. In 2017.2 onespin was defined for anything that wasnt the Xilinx simulator. Now there are many other cases covered. The only real workaround was to hook into GSR from VHDL (which is a kludge) and just avoid the reset from it. Luckily this is only needed in the dual clock XPM FIFO (as it uses the CDC which is the main problem).

As I posted, I take issue with Xilinx arbitrarily picking 100ns as a reset period (it might change in a future version). Im only doing a functional simulation, GSR should not be needed at all, or I should be able to provide it from a testbench.

I too am frustrated with XPM. We only have a single mixed-mode licence, and there is now pressure to not use XPM because of it, and use coregen instead. This is very annoying because in my latest design:

1. I need to support KU and KUP parts.

2. I need to support single clock and dual clock modes

3. I need same width and mixed width modes

All of the above would be covered by XPM. Instead Im going to need about 8 coregen files. But not only that, I need to generate the sim model and check them into git separately, meaning you've easily got the possibility of having your .xci and .vhd sim model out of sync with each other.

XPM was a long awaited solution to answer the lack of libraries like altera's. Altera have had the equivolent of XPM (and more) for as long as Ive been an engineer (15 years) or more.

Tags (1)
Highlighted
Scholar
Scholar
1,867 Views
Registered: ‎04-26-2012

@richardhead   "This just doesnt work (I tried). Stuff just doesnt initialise properly."

OK- I don't have an Aldec mixed language license to experiment with, but when I looked at the XPM code, it appeared that all references to glblGSR_xpmcdc within  xpm_cdc.sv were themselves inside an `ifdef XPM_CDC_BHVSIM_ONLY, so I don't know why there would be an initialization issue when defining the ONESPIN macro unless something is broken elsewhere in the XPMs.

EDIT1: I just looked at xpm_cdc.sv in 2019.1, there are two `ifdef XPM_CDC_BHVSIM_ONLY macros that are missing `else clauses to handle initialization properly...

EDIT2: and many of the macros that do have an 'else clause don't use the register reset lines or check INIT_SYNC_FF...

> All of the above would be covered by XPM. Instead Im going to need about 8 coregen files.

I've been avoiding XPMs by writing my own inferenced memories and FIFOs, which are much more portable than the Xilinx stuff; if things don't infer correctly, I still prefer a wrappered primitive over the coregen stuff.

After posting this thread back in 2017, I did hear from a Xilinx marketing type asking for clarification of why SV-mixed-license-only device libraries were a bad thing, but it doesn't appear that any action was ever taken to resolve this tool regression from the older UNIMACROs.

-Brian

 

 

 

Highlighted
1,026 Views
Registered: ‎08-14-2008

I just stumbled on your issue. Have you tried icarus verilog? It has a verilog to vhdl translator that might work to translate the system verilog to vhdl https://iverilog.fandom.com/wiki/Using_VHDL_Code_Generator
0 Kudos
Highlighted
Teacher
Teacher
989 Views
Registered: ‎07-09-2009

Thats an interesting tool. Im going to have a look

On the down side, most companies I work for, you are not allowed to install programs without a lot of IT paper work, justifications and cost,

so it would be great if Xilinx returned to having VHDL and Verilog IP / examples,

Wonder if Xilinx have not the people to support VHDL, if Xilinx would purchase the tools needed to do auto conversion and publish the results,

They should have dual VHDL / Verilog tool and regression tests, so they can put the VHDL and the verilog through the same regresion tests,
<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
0 Kudos
Highlighted
972 Views
Registered: ‎08-14-2008

I gave the hail mary try at home last night. iverilog had a lot of errors and bailed on trying to translate.