09-17-2014 05:23 PM
I try to simply simulate a RAM generated by block memory generator 8.2 in order to verify the latency of the read port.
The project was compiled with no warning, no error, and the simulated with no warning, no error. But when I read the same address of the RAM (the address was written before), there were always no output, and fixed to all 0's.
Attachment is my project.
09-17-2014 11:38 PM
I assume that you are talking about port 'doutb' and if YES, then there is slight mistake on port mapping. At present, the design file 'RAM_TEST/RAM_TEST.srcs/sources_1/new/TOP.v' contain ports declaration as
< input [7:0] addra,
< input [8:0] dina,
Change them to
> input [8:0] addra,
> input [7:0] dina,
And with this you should see the correct o/p.
09-18-2014 12:35 AM - edited 09-18-2014 01:41 AM
It looks you generated the IP with VHDL as target language but the top level and tb are in Verilog, so GSR might not cause issue
But the top level port signals do not match that of core .vho file, either regenate the core as per your top level addr and data width or change the port mappings
Hope this helps
09-18-2014 01:57 AM
Thank u very much!
What a terrible mistake to an engineer.
I have changed the ports declaration, and also fix the ports width mismatch in RAM_SIM.v. But the doutb still fixed to ALL 0s in .
My Vivado version is 2014.1
09-18-2014 01:58 AM
Did you drive the data after 100ns of initial delay and still not seeing proper output?
09-18-2014 02:03 AM - edited 09-18-2014 02:04 AM
I used 2014.2, changing the port mis match solved the issue, did't change anything in RAM_SIM.v you can see the snapshot in my earlier post
09-18-2014 12:13 PM
I have changed the ports declaration, rebuilded a new project, and also fixed the ports width mismatch in RAM_SIM.v. But the doutb still fixed to ALL 0s in Functional and Timing simulations.
Only in Behavioral simulation, all seems to right. Did I miss anything during Functional and Timing simulations?
09-19-2014 09:38 AM
@carnby can you tell us your exact steps followed to perform Functional and Timing Simulations?
09-19-2014 06:42 PM
I simulated my design through GUI command in Vivado.
I first run the Synthesis, and then run the Implementation. After that, I directly run the timing simulation through press "Run Post-Implementation Timing Simulation" button.
I run the Functional simulation in the same way.
All other settings about Sythesis, Implementation and Simulation are default.