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carnby
Explorer
Explorer
10,553 Views
Registered: ‎11-23-2013

no output of RAM generated by block memory generator 8.2

Hello,

 

I try to simply simulate a RAM generated by block memory generator 8.2 in order to verify the latency of the read port.

 

The project was compiled with no warning, no error, and the simulated with no warning, no error. But when I read the same address of the RAM (the address was written before), there were always no output, and fixed to all 0's.

 

Attachment is my project.

 

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8 Replies
dprasad
Xilinx Employee
Xilinx Employee
10,535 Views
Registered: ‎09-13-2014

Hi,

 

I assume that you are talking about port 'doutb' and if YES, then there is slight mistake on port mapping. At present, the design file 'RAM_TEST/RAM_TEST.srcs/sources_1/new/TOP.v' contain ports declaration as

 

< input [7:0] addra,
< input [8:0] dina,

 

Change them to 

 

> input [8:0] addra,
> input [7:0] dina,

 

And with this you should see the correct o/p.

 

--dhiRAj

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vsrunga
Xilinx Employee
Xilinx Employee
10,521 Views
Registered: ‎07-11-2011

HI,

 

It looks you generated the IP with VHDL as target language but the top level and tb are in Verilog, so GSR might not cause issue

But the top level port signals do not match that of core .vho file, either regenate the core as per your top level addr and data width or change the port mappings

 

RAM.png

 

 

Hope this helps

 

Regards,

Vanitha

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carnby
Explorer
Explorer
10,509 Views
Registered: ‎11-23-2013

Thank u very much!

What a terrible mistake to an engineer.

 

I have changed the ports declaration, and also fix the ports width mismatch in RAM_SIM.v. But the doutb still fixed to ALL 0s in .

My Vivado version is 2014.1

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yenigal
Xilinx Employee
Xilinx Employee
10,506 Views
Registered: ‎02-06-2013

 

Hi

 

Did you drive the data after 100ns of initial delay and still not seeing proper output?

Regards,

Satish

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vsrunga
Xilinx Employee
Xilinx Employee
10,498 Views
Registered: ‎07-11-2011

HI,

 

I used 2014.2, changing the port mis match solved the issue, did't change anything in RAM_SIM.v you can see the snapshot in my earlier post

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carnby
Explorer
Explorer
10,474 Views
Registered: ‎11-23-2013

I have changed the ports declaration, rebuilded a new project, and also fixed the ports width mismatch in RAM_SIM.v. But the doutb still fixed to ALL 0s in Functional and Timing simulations.

 

Only in Behavioral simulation, all seems to right. Did I miss anything during Functional and Timing simulations?

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vsrunga
Xilinx Employee
Xilinx Employee
10,457 Views
Registered: ‎07-11-2011

@carnby can you tell us your exact steps followed to perform Functional and Timing Simulations?

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carnby
Explorer
Explorer
10,446 Views
Registered: ‎11-23-2013

Hi vsrunga,

I simulated my design through GUI command in Vivado.

I first run the Synthesis, and then run the Implementation. After that, I directly run the timing simulation through press "Run Post-Implementation Timing Simulation" button.

I run the Functional simulation in the same way.

 

All other settings about Sythesis, Implementation and Simulation are default.

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