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Visitor deba_techno
Visitor
8,766 Views
Registered: ‎10-26-2011

problem in fft1024 in simulation

sir, i have simulated the follwing testbench code for 1024 point fft for 50000ns. but i get the output where input is undefined. below is the testbench code

 

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use std.textio.all;
use IEEE.std_logic_textio.all;

entity tb_cfft1024x12 is

end tb_cfft1024x12;

architecture tb of tb_cfft1024x12 is

component cfft1024X12
         port(
                 clk : in STD_LOGIC;
                 rst : in STD_LOGIC;
                 start : in STD_LOGIC;
                 invert : in std_logic;
                 Iin : in STD_LOGIC_VECTOR(11 downto 0); -------------- real input
                 Qin : in STD_LOGIC_VECTOR(11 downto 0); -----------imaginary inout
                 inputbusy : out STD_LOGIC;
                 outdataen : out STD_LOGIC;
                 Iout : out STD_LOGIC_VECTOR(13 downto 0); -----------real output
                 Qout : out STD_LOGIC_VECTOR(13 downto 0);-------------imaginary output

OutPosition : out STD_LOGIC_VECTOR( 9 downto 0 )
             );
end component;

signal  clk : STD_LOGIC;
signal  rst : STD_LOGIC;
signal  start : STD_LOGIC;
signal  invert : std_logic;
signal  Iin : STD_LOGIC_VECTOR(11 downto 0);
signal  Qin : STD_LOGIC_VECTOR(11 downto 0);
signal  inputbusy : STD_LOGIC;
signal  outdataen : STD_LOGIC;
signal  Iout : STD_LOGIC_VECTOR(13 downto 0);
signal  Qout : STD_LOGIC_VECTOR(13 downto 0);
signal  output_position:std_logic_vector(9 downto 0 );
constant clkprd : time:=10 ns;
begin
f: cfft1024x12 port map(clk=>clk,
                        rst =>rst,
                        start=> start,
                        invert=>invert,
                        Iin=>Iin,
                        Qin=>Qin,
                        inputbusy=>inputbusy,
                        outdataen=>outdataen,
                        Iout=>Iout,
                        Qout=>Qout,
                        OutPosition=>output_position);

clockgen: process
begin
        clk <= '1';
        wait for clkprd/2;
        clk <= '0';
        wait for clkprd/2;
end process;

fileread: process
file FileIn1 : text is in  "bindata.txt"; -- bindata is a file containing 1-1024 in binary.
variable LineIn1   : line;
variable InputTmp1 :std_logic_vector(11 downto 0);
begin
                rst<='1';
                wait until clk'EVENT and clk='1';
                rst<='0';
                wait until clk'EVENT and clk='1';
                invert<='0';
                start<='1';
                wait until clk'EVENT and clk='1';
                start<='0';

                while  not( endfile( FileIn1)) loop
                        readline( FileIn1, LineIn1);
                        read(LineIn1, InputTmp1);
                        Iin<=InputTmp1;
                        Qin<="000000000000";
                        wait until clk'EVENT and clk='1';
                end loop;

                wait until outdataen'EVENT and outdataen='1';
                wait for 15000 ns;
end process;

cfft1024.JPG

               


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9 Replies
Explorer
Explorer
8,760 Views
Registered: ‎04-09-2008

Re: problem in fft1024 in simulation

Try setting all of the inputs before you take the core out of reset?

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Visitor deba_techno
Visitor
8,748 Views
Registered: ‎10-26-2011

Re: problem in fft1024 in simulation


@pcurt wrote:

Try setting all of the inputs before you take the core out of reset?


sir, i have simulated the code for 100 ns clk period (previous in code clk = 10 ns). got the same output.and i also don't understand sir, what do u want to mean. i have already sent my testbench code. can plz indicate the line where i have to modify it to get the correct simulation plot.

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Visitor deba_techno
Visitor
8,740 Views
Registered: ‎10-26-2011

Re: problem in fft1024 in simulation

sir, my problem is urjent. plz suggest.

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Teacher eteam00
Teacher
8,737 Views
Registered: ‎07-21-2009

Re: problem in fft1024 in simulation

If your problem is urgent, suggest you open a webcase for direct Xilinx applications support, or contact a local Xilinx field applications engineer.

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
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Scholar joelby
Scholar
8,727 Views
Registered: ‎10-05-2010

Re: problem in fft1024 in simulation

Since lin is set by InputTmp1, which is set by read(), maybe there's something bad on the last line of your bindata.txt file? Make sure it doesn't have any extra rubbish at the end.

 

If read() is returning 'undefined' for some other perfectly good reason (I don't know! I don't use VHDL), you could add a condition to check this before assigning lin from InputTmp1, e.g.

 

if (InputTmp1 == 'UUUUUUUU') then
  lin <= 0;
else
  lin <= InputTmp1;
end if

 

(warning: this is pseudocode)

 

Highlighted
Teacher rcingham
Teacher
8,723 Views
Registered: ‎09-09-2010

Re: problem in fft1024 in simulation

if is_X(InputTmp1) then

  lin <= (others => '0');

else

  lin <= ImputTmp1;

end if;

 



------------------------------------------
"If it don't work in simulation, it won't work on the board."
Visitor deba_techno
Visitor
8,716 Views
Registered: ‎10-26-2011

Re: problem in fft1024 in simulation


@rcingham wrote:

if is_X(InputTmp1) then

  lin <= (others => '0');

else

  lin <= ImputTmp1;

end if;

 



@thank you vary much both @ joelby sir, and @ rcingham sir. I have modified my testbench code following your instruction and get the waveform

1024 fft.JPG

 

It means, fft processor takes time to give output after loading the input data from text file. but i have test  it for real data. sir, if i want to test for imaginary data also, will i have to generate another text file for imaginary data, if so, i am little confused how will i assign it to Qin (imaginary data). plz suggest.

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Scholar joelby
Scholar
8,713 Views
Registered: ‎10-05-2010

Re: problem in fft1024 in simulation

Just use a second file containing imaginary values:

 

readline( FileIn1, LineIn1);
readline( FileIn2, LineIn2);
read(LineIn1, InputTmp1);
read(LineIn2, InputTmp2);
Iin<=InputTmp1;
Qin<=InputTmp2;

 Or you could alternate I and Q values in the single file:

 

readline( FileIn1, LineIn1);
read(LineIn1, InputTmp1);
Iin<=InputTmp1;

readline( FileIn1, LineIn1);
read(LineIn1, InputTmp1);
Qin<=InputTmp1;

 etc.

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Newbie kerry123
Newbie
8,627 Views
Registered: ‎07-24-2012

Re: problem in fft1024 in simulation

I'm not at all getting any output...Please could anyone help me....this might be because of syniplify library...I had commented the syniplify library in blockdram...

My inputs are getting loaded/read...but there are no outputs and the outenable is not high at any time..please could anyone help me...I needed this very urgent..

 

Deba_techno..please could you help me...

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