cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
Visitor
Visitor
380 Views
Registered: ‎11-26-2018

simulate vivado design from questasim gui

I have a vivado design that uses multiple xilinx cores, including a clock wizard generated core, fifos and memory, and a tristate ethernet core.  I would like to launch a simulation from Questasim without starting vivado.  What files need to be referenced for vcom and vlog to get a good simulation compile from questasim.

Please let me know for the memories, the clock and the ethernet core.

Thanks

Fred Skalka

Tags (2)
0 Kudos
1 Reply
Highlighted
Scholar
Scholar
342 Views
Registered: ‎08-01-2012

Re: simulate vivado design from questasim gui

IP cores should have a <corename>_sim_netlist.v/vhdl file in their folders. These are the only files you need to compile, assuming all you want is an RTL simulation.

But be wary. I have a 10G mac core, and the simulation netlist is a 40mb text file. Its probably going to be VERY slow to simulate. Usuaully more productive just to model the interface.

0 Kudos