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Newbie
Newbie
10,086 Views
Registered: ‎01-11-2016

simulating vhdl 2008 in vivado 2015.4

Hi,

 

I use vivado 2015.4, and I have a very simple vhdl 2008 source (I use ieee.fixed_pkg.all).

I can successfully synthesize but I cannot simulate.

 

The error is:

ERROR: [XSIM 43-4187] File "/proj/xcohdstaff/fengc/head/HEAD/data/vhdl/src/ieee_2008/fixed_pkg.vhdl" Line 45 : The "Vhdl 2008 Package Instantiation Declaration" is not supported yet for simulation.

 

I thought vhdl 2008 was supported due to AR# 62678

"We are not planning to support any VHDL-2008 constructs in the Vivado Simulator until 2015.3. In 2015.3, we have scheduled to support new package as well as few ease of use features."

 

There is something I forgot, or something wrong?

There is some work around?

 

best regards

Max

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Moderator
Moderator
10,079 Views
Registered: ‎01-15-2008

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Xilinx Employee
Xilinx Employee
10,056 Views
Registered: ‎09-13-2014

For VHDL-2008, only a limited set of feauture is supported in Vivado Simulator. From your ERROR message, it seems that you have something like

_________

library ieee;
use ieee.fixed_pkg.all;

entity top is
end;

architecture arch of top is
begin
end;

_______

The moment you use 'fixed_pkg', it means that you are using package instantiation as fixed_pkg is nothing but instance of generic package like

_________

 

library IEEE;

package fixed_pkg is new IEEE.fixed_generic_pkg
generic map (
fixed_round_style => IEEE.fixed_float_types.fixed_round,
fixed_overflow_style => IEEE.fixed_float_types.fixed_saturate,
fixed_guard_bits => 3,
no_warning => false
);

_________

So those features, which are not supported, you should see ERROR message ID 43-4187. If your intention is not to use the fixed_pkg, please modify your test case.

 

--dhiRAj

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Teacher
Teacher
10,048 Views
Registered: ‎07-09-2009

its less than a decade since 2008,
your optimism is welcome but miss placed.
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Adventurer
Adventurer
8,111 Views
Registered: ‎04-25-2016

I just have added video timing IP in my bloack diagram and I also worte a test bench to simulate the design but I am facing syntax problem for a simple counter using signals in test bench. 

 

Kindly let me that Vivado 2015.4 support VHDL 2008 or not ? 

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Adventurer
Adventurer
8,108 Views
Registered: ‎04-25-2016

Following is the error which I got while simulating  vivado 2015.4. 

 

ERROR: [VRFC 10-1449] this construct is only supported in VHDL 1076-2008 [D:/Projects_and_Simulations/Xilinx_Vivado_Projects/Part 116 Test Pattern Generation/project_2/project_2.srcs/sim_1/new/design_1_wrapper_tb.vhd:201]

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Xilinx Employee
Xilinx Employee
8,098 Views
Registered: ‎09-13-2014

Please make sure that you are setting the file type fpr 'design_1_wrapper_tb.vhd:' as VHDL-2008.

 

--dhiRAj

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Visitor
Visitor
676 Views
Registered: ‎06-04-2019

The state of current toolchain and vendor inertia is quite sad.

If Xilinx there is bussiness value in developing and maintaining toolchain, please make a joint effort with Lattice and Intel and open source tools so that at least the users who suffer the pain of toolchain can contribute to the end of their suffering.

As a proposal, why not just officially support GHDL or any equivalent project and apply a fraction of the money used to maintain Vivado Simulator?
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Moderator
Moderator
654 Views
Registered: ‎04-24-2013

Hi @expertengr 

VHDL-2008 support in 2015.4 was in very early access, you can see what was support in the 2015.4 version of UG900, Appendix E available here

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2015_4/ug900-vivado-logic-simulation.pdf

Later versions of the tools improved support but it is still not comprehensive.

Best Regards
AIdan

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Teacher
Teacher
646 Views
Registered: ‎07-09-2009

just a note if you are thinking of changin vivado versions

 

when they say "not comprehensive" ,   think politician speak.. ( Boris johson in the UK ? )

      one day....

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