01-11-2016 03:01 AM
I use vivado 2015.4, and I have a very simple vhdl 2008 source (I use ieee.fixed_pkg.all).
I can successfully synthesize but I cannot simulate.
The error is:
ERROR: [XSIM 43-4187] File "/proj/xcohdstaff/fengc/head/HEAD/data/vhdl/src/ieee_2008/fixed_pkg.vhdl" Line 45 : The "Vhdl 2008 Package Instantiation Declaration" is not supported yet for simulation.
I thought vhdl 2008 was supported due to AR# 62678
"We are not planning to support any VHDL-2008 constructs in the Vivado Simulator until 2015.3. In 2015.3, we have scheduled to support new package as well as few ease of use features."
There is something I forgot, or something wrong?
There is some work around?
01-11-2016 03:14 AM - edited 01-11-2016 03:21 AM
can you check if the following AR helps
refer chapter-5 in the following link
also check appendix e from the following link
01-11-2016 03:57 AM
For VHDL-2008, only a limited set of feauture is supported in Vivado Simulator. From your ERROR message, it seems that you have something like
entity top is
architecture arch of top is
The moment you use 'fixed_pkg', it means that you are using package instantiation as fixed_pkg is nothing but instance of generic package like
package fixed_pkg is new IEEE.fixed_generic_pkg
generic map (
fixed_round_style => IEEE.fixed_float_types.fixed_round,
fixed_overflow_style => IEEE.fixed_float_types.fixed_saturate,
fixed_guard_bits => 3,
no_warning => false
So those features, which are not supported, you should see ERROR message ID 43-4187. If your intention is not to use the fixed_pkg, please modify your test case.
01-11-2016 04:55 AM
04-25-2016 05:44 AM
I just have added video timing IP in my bloack diagram and I also worte a test bench to simulate the design but I am facing syntax problem for a simple counter using signals in test bench.
Kindly let me that Vivado 2015.4 support VHDL 2008 or not ?
04-25-2016 05:55 AM
Following is the error which I got while simulating vivado 2015.4.
ERROR: [VRFC 10-1449] this construct is only supported in VHDL 1076-2008 [D:/Projects_and_Simulations/Xilinx_Vivado_Projects/Part 116 Test Pattern Generation/project_2/project_2.srcs/sim_1/new/design_1_wrapper_tb.vhd:201]
04-25-2016 08:58 AM
Please make sure that you are setting the file type fpr 'desi
06-24-2019 01:32 AM
06-26-2019 02:02 AM
VHDL-2008 support in 2015.4 was in very early access, you can see what was support in the 2015.4 version of UG900, Appendix E available here
Later versions of the tools improved support but it is still not comprehensive.
06-26-2019 02:12 AM
just a note if you are thinking of changin vivado versions
when they say "not comprehensive" , think politician speak.. ( Boris johson in the UK ? )