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Registered: ‎10-06-2011

simulation on command prompt



I have a verilog file (say a1.v) and its test bench (say ta1.v). I want to simulate and verify the inputs and outputs of this test bench using  linux command prompt. Please tell me the procedure to simulate verilog code using command prompt (not GUI). I hvae been using ISE 13.1 tool.

I have tried following procedure  on linux command prompt:


vlogcomp a1.v ta1.v  

fuse work.a1 work.ta1  -L unisims_ver -L unimacro_ver -L xilinxcorelib_ver


(after this executable file has been generated  called x.exe )


Later i am not able to run x.exe file and how to verify inputs and outputs ???

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Advisor joelby
Registered: ‎10-05-2010

Re: simulation on command prompt

I'm sure there's a good way to do this with ISim, but you may also be able to use the free Icarus Verilog simulator - it works well in this sort of scenario.
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