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david.rios
Visitor
Visitor
895 Views
Registered: ‎07-26-2018

simulation problem with vivado simulator [VRFC 10-453] cannot open verilog file

Hi,

i was simulating my design until this error happen:

[VRFC 10-453] cannot open verilog file

[VRFC 10-453] cannot open vhdl file

i'm in a linux machine. I was able to simulate, i did not change any path in my directories. Does anyone knows what can be the problem?

I can synthesize and run the implementation. Even the bit stream is ok. But i can not simulate.

Any ideas?

Thanks in advance

David

 

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shameera
Moderator
Moderator
852 Views
Registered: ‎05-31-2017

Hi @david.rios,

Can you please give a try by simulating one of the example designs and let us know if you are facing the same issue for example design too.

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david.rios
Visitor
Visitor
828 Views
Registered: ‎07-26-2018

Hi,

I can actually simulate other designs. I used a new project and took only parts of my design and i'm able to simulate. If you can tell me what can be the problem, i will not have to do a new project to simulate it.

thanks

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