12-13-2018 02:16 AM
i was simulating my design until this error happen:
[VRFC 10-453] cannot open verilog file
[VRFC 10-453] cannot open vhdl file
i'm in a linux machine. I was able to simulate, i did not change any path in my directories. Does anyone knows what can be the problem?
I can synthesize and run the implementation. Even the bit stream is ok. But i can not simulate.
Thanks in advance
12-14-2018 05:08 AM
12-17-2018 11:59 PM
I can actually simulate other designs. I used a new project and took only parts of my design and i'm able to simulate. If you can tell me what can be the problem, i will not have to do a new project to simulate it.