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Visitor fbartra
Visitor
1,786 Views
Registered: ‎10-27-2010

synthesis signal names

is there a detail document of how the internal signals are named during synthesis? Spartan FPGA

it is very difficult to follow during simulation

I could not find anything in your user guides/manuals

 

Thank you

Fausto Bartra

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2 Replies
Xilinx Employee
Xilinx Employee
1,733 Views
Registered: ‎08-01-2008

Re: synthesis signal names

use keep hierarchy option in synthesis property
Thanks and Regards
Balkrishan
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Contributor
Contributor
1,716 Views
Registered: ‎02-18-2015

Re: synthesis signal names

@balkris
Does the Keep Hierarchy option, aborts any optimizations made by the tool on the IP?

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