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sai_shashi
Explorer
Explorer
4,285 Views
Registered: ‎07-25-2016

using sinusoids in simulation

Hi there,

I need to use sine and cosine as inputs to my DUT through test-bench. I have no clue on how to accomplish this. can anybody please guide me on this..?

 

Thanks in advance

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5 Replies
hpoetzl
Voyager
Voyager
4,277 Views
Registered: ‎06-24-2013

Hey @sai_shashi

 

Really depends on the language (C, C++, VHDL, Verilog) and tools (Vivado, HLS, GHDL, etc) you are using and at what level the simulation happens.

 

Best,

Herbert

-------------- Yes, I do this for fun!
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sai_shashi
Explorer
Explorer
4,259 Views
Registered: ‎07-25-2016

Thanks for the reply,

 

I am using SystemVerilog testbench.

I am simulating in Vivado environment.

I am simulating the design before the synthesis.

 

Thanks

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dpaul24
Scholar
Scholar
4,258 Views
Registered: ‎08-07-2014

You can use VHDL/Verilog to code for Taylor series expansion up to 3 terms. It generates fairly accurate sine and cosine waveforms.

 

https://en.wikipedia.org/wiki/Taylor_series#Trigonometric_functions

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bruce_karaffa
Scholar
Scholar
4,254 Views
Registered: ‎06-21-2017

I prefer to read my test bench signal inputs from a text file.  This provides a lot of flexibility since it's easy to create different frequency sinusoids, add noise, etc.  Matlab is good for this, but in a pinch, you can use Excel or a Matlab clone like Scilab. 

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hpoetzl
Voyager
Voyager
4,253 Views
Registered: ‎06-24-2013

@sai_shashi

 

For the test bench, something like this should suffice (untested):

const real pi = 3.14159265359;

real freq = 1e3; real offset = 0.5; real ampl = 0.3; real sine_out; always @(sampling_clock) begin sine_out = offset + (ampl * sin(2 * pi * freq * $time * 1e-12)); $write("Sine value at time=%0g is =%0g\n", $time, sine_out); end

Hope it helps,

Herbert

-------------- Yes, I do this for fun!
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