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9,836 Views
Registered: ‎06-16-2014

using vivado simulator xsim in batch mode

I am trying to run a vhdl simulation that uses a verilog DDR memory model. I have the files listed in *.prj file, which i then call via xelab,   xelab command i am using is

xelab -prj xsim.prj  -s sim_snapshot xil_defaultlib.testbench

verilog xil_defaultlib -sourcelibdir .
verilog xil_defaultlib -sourcelibext  vh
verilog xil_defaultlib -sourcelibfile 1024Mb_mobile_ddr_parameters.vh
verilog xil_defaultlib +define+den1024Mb +define+sg5 +define+x16 +define+FULL_MEM mobile_ddr.v

 

but this does not work,  can you explain what i need to do please.

 

Thanks Mike

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Teacher
Teacher
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Registered: ‎03-31-2012

"it does not work" is very unhelpful. At each individual stage, what do you expect and what happens? What "does not work" ?

Also you show only the ddr verilog model portion of the prj file. Where is the rest ? specifically the vhdl files etc. ?
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9,828 Views
Registered: ‎06-24-2015

Hi mikeyates@icloud.com,

 

You need to first compile the verilog file, then elaborate and then simulate. So you will need to run xvlog first, then xelab, and finally xsim. 

 

Refer to page 120 of this link:
http://www.xilinx.com/support/documentation/sw_manuals/xilinx2015_1/ug900-vivado-logic-simulation.pdf

 

Thanks,
Nupur

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Registered: ‎06-16-2014

The other files compile ok, it is just loading the ddr parameter file that is the problem, have you used xsim when you have a ddr memory model. if so can you send an example.. Thanks

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Registered: ‎06-16-2014

Have you used the xsim to simulate a design with a ddr verilog model? if so please send exaple how to load the parameter from the .vh file.

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Teacher
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Registered: ‎03-31-2012

@nupurs:
from ug900: "xelab can implicitly call the parsing commands, xvlog and xvhdl."
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Teacher
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Registered: ‎03-31-2012

again: what is the problem you see? probably ddr.v can't find the vh file? (is it included in there?) normally you don't load vh files separately. You let the include find it. If include is not finding it, you need to add --include in the xelab command line.
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Registered: ‎06-16-2014

Have you used a ddr for simulation, I have read all the documentation. Again have you any experience of pulling a verilog model and setting it ip. I normally do this with modelsim.

 

Cheers

Mike

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9,810 Views
Registered: ‎06-16-2014

I will give that a go. Have you tried this in vivado, I normally use modelsim.

Cheers

Mike

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