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Visitor
Visitor
6,450 Views
Registered: ‎07-15-2011

verilog $strobe or $display do not always display result. in Vivado 2016.2

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I am writing a verilog testbench and find that when the $display or $strobe system tasks are used to display a message I don't always get an output on the tcl console. I'm using the Vivado 2016.2 simulator and I can see that the calculations are always done and I can manually see that everything is correct in the waveform viewer. If I Restart the simulator multiple times, (i.e. run for 0 again but not recompile), I sometimes I see the messages and sometimes I don't.

 

Anyone else seen this behavior or is it something wrong with my code?

 

Thanks in advance

 

Jonathan 

 

module check_clock_frequency
(
reset,
clk,
check_now,
display_freq,
expected, //expected frequency
ppm, //allowed error in measurement in parts per Million
msg, //message string
bt_frequency,
done
);

parameter MSGLENGTH=12 ;
input reset;
input clk;
input check_now;
input display_freq;
input [63:0] expected; //expected frequency
input [63:0] ppm; //allowed error in measurement in parts per Million
input [8*MSGLENGTH:1] msg; //message string
output [63:0] bt_frequency;
output done;


real t0;
real t1;
real error;
real min;
real max;
real re_expected;
real re_ppm;

real frequency;
reg [63:0] bt_frequency_q;
reg done_q;

always@*
begin
if (reset)
done_q=1'b0;
else
begin
if (check_now)
begin
@ (posedge clk) t0 = $realtime; //get rising edge of clock time
@ (posedge clk) t1 = $realtime; //and the next one
frequency = 1.0e9 / (t1 - t0);
bt_frequency_q = $realtobits(frequency); //must be a vector to send out and output port
if (display_freq)
$display("Frequency = %g", frequency);
//check if in range
re_expected=$bitstoreal(expected);
re_ppm =$bitstoreal(ppm);
error = re_expected *re_ppm; //error is in hz
min = (re_expected*1e6) - error;
max = (re_expected*1e6) + error;
if ((frequency < min) || (frequency>max) )
begin
// $display ("%0s", msg) ;
//$display("%t ns : FAIL %0s :Frequency out of range: frequency = %f Hz, min = %f , max = %f ", $time/1000, msg, frequency/1e6, min/1e6, max/1e6) ;
$strobe("%t ns : FAIL %0s :Frequency out of range: frequency = %f Hz, min = %f , max = %f ", $time/1000, msg, frequency/1e6, min/1e6, max/1e6) ;
end
else
begin
//$display ("%0s", msg) ;
//$display("%t ns: PASS %0s :Frequency in range: frequency = %f Hz, min = %f , max = %f ", $time/1000, msg, frequency/1e6, min/1e6, max/1e6);
$strobe("%t ns: PASS %0s :Frequency in range: frequency = %f Hz, min = %f , max = %f ", $time/1000, msg, frequency/1e6, min/1e6, max/1e6);
end
done_q = 1'b1;
end
else
begin
bt_frequency_q = bt_frequency_q;
done_q=1'b0;
end
end //if reset
end //always

assign done=done_q;
assign bt_frequency=bt_frequency_q;
endmodule

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Observer
Observer
10,594 Views
Registered: ‎08-10-2009

Re: verilog $strobe or $display do not always display result. in Vivado 2016.2

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You don't show the external portion of your testbench that instantiates this module. Is it your $display or $strobe (or both?) that sometimes doesn't get displayed? What controls the beginning and end of simulation? A $strobe displays just like $display except it waits until all events are finished. Is it possible that an external process is terminating the simulation before the simulator gets around to acting on the $strobe?

 

It would help if you described your signaling during a simulation run. I assume the check_now pulse controls each measurement/display sequence. How often does check_now occur? How wide is its pulse?

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4 Replies
Observer
Observer
10,595 Views
Registered: ‎08-10-2009

Re: verilog $strobe or $display do not always display result. in Vivado 2016.2

Jump to solution

You don't show the external portion of your testbench that instantiates this module. Is it your $display or $strobe (or both?) that sometimes doesn't get displayed? What controls the beginning and end of simulation? A $strobe displays just like $display except it waits until all events are finished. Is it possible that an external process is terminating the simulation before the simulator gets around to acting on the $strobe?

 

It would help if you described your signaling during a simulation run. I assume the check_now pulse controls each measurement/display sequence. How often does check_now occur? How wide is its pulse?

View solution in original post

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Highlighted
Visitor
Visitor
6,191 Views
Registered: ‎07-15-2011

Re: verilog $strobe or $display do not always display result. in Vivado 2016.2

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Both the $display and the $strobe don't always get displayed on the tcl console, but you comment about the check_now pulse made me look at it more closely. I was returning a handshake via "done" to deassert the check_now signal and I had no delay,hence the randomness. 

 

Thanks for taking the time

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Highlighted
Observer
Observer
5,007 Views
Registered: ‎08-24-2015

Re: verilog $strobe or $display do not always display result. in Vivado 2016.2

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I am seeing similar symptoms.  Any resolution to this?

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Observer
Observer
4,994 Views
Registered: ‎08-24-2015

Re: verilog $strobe or $display do not always display result. in Vivado 2016.2

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When I was seeing this issue I was using 2016.1 on Linux virtualbox.

 

I switched to 2016.4 on Windows 7 and I am not seeing this issue with $display intermittently not printing... maybe it was fixed after 2016.2.

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