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Contributor
Contributor
621 Views
Registered: ‎12-06-2018

vhdl program

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this is the program in vhdl and i have to get the output waveforms   for this  logic :

data<="1010101111001101" when data_count="00" else
      "1110110111110001" when data_count="01" else
      "1100110100010010" when data_count="10" else
      "1010110100000001" when data_count="11";
        

and the program is as shown below:

entity counter_sequence1 is
    Port ( clk : in  STD_LOGIC;
           reset : in  STD_LOGIC;
           dout : out  STD_LOGIC);
end counter_sequence1;

architecture Behavioral of counter_sequence1 is
signal count  : integer range 0 to 15:= 0;
signal data  : std_logic_vector (15 downto 0);
signal data_count:std_logic_vector(1 downto 0); 
--signal enable:std_logic;
--signal terminate:std_logic; 
begin
process(clk,reset)
begin
    if reset='1' then
        dout <= '0';
     elsif rising_edge(clk) then
     if count < 16 then
        dout <= data(15-count);
    end if;
    end if;
end process;

process(clk,reset)         
begin  
    if (reset='1') then          
        count<= 0;          
    elsif(clk'event and clk='1') then
        count <= count + 1; 
        --enable<='1';
        end if;
end process;
process(clk,reset)         
begin  
    if (reset='1') then          
        data_count<= "00";         
    elsif(clk'event and clk='1') then
        data_count <= data_count + 1;
        --if (enable<='1') then
--<=data+1;
    end if;
    end if;
end process;

data<="1010101111001101" when data_count="00" else
      "1110110111110001" when data_count="01" else
      "1100110100010010" when data_count="10" else
      "1010110100000001" when data_count="11";
        
end Behavioral

but I'm not getting the output .pls verify .

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Scholar richardhead
Scholar
599 Views
Registered: ‎08-01-2012

Re: vhdl program

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You're getting what output? and where (simulation or on chip)? what do you expect? whats the problem?

You also didnt post the whole code.

10 Replies
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Scholar richardhead
Scholar
600 Views
Registered: ‎08-01-2012

Re: vhdl program

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You're getting what output? and where (simulation or on chip)? what do you expect? whats the problem?

You also didnt post the whole code.

Explorer
Explorer
598 Views
Registered: ‎03-17-2011

Re: vhdl program

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@farhathsuj

the way you ask it, you won't likely have answers. Don't expect people to do your job.

--Sebastien
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Contributor
Contributor
586 Views
Registered: ‎12-06-2018

Re: vhdl program

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i was just asking help not more than that
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Contributor
Contributor
570 Views
Registered: ‎12-06-2018

Re: vhdl program

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for the above program im getting the output as shown below:

 

2019-01-29.png
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Explorer
Explorer
565 Views
Registered: ‎03-17-2011

Re: vhdl program

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Ok for the screenshot of the simulator. I see dout is changing.

What's your problem?

 

--Sebastien
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Scholar richardhead
Scholar
554 Views
Registered: ‎08-01-2012

Re: vhdl program

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Without saying what the problem is - no one can help.

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Contributor
Contributor
513 Views
Registered: ‎12-06-2018

Re: vhdl program

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i want to generate the pulse for below specifications
data<="1010101111001101" when data_count="00" else
"1110110111110001" when data_count="01" else
"1100110100010010" when data_count="10" else
"1010110100000001" when data_count="11";
but im not getting dout as above.
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Scholar richardhead
Scholar
508 Views
Registered: ‎08-01-2012

Re: vhdl program

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@farhathsuj

Your post still makes no sense? you get no dout like in the picture? you get no dout like you expect (what do you expect)?

You still havent posted what the actual problem is.

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Contributor
Contributor
500 Views
Registered: ‎12-06-2018

Re: vhdl program

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i want to gerate the pulse one after another pulses for below values
"1010101111001101" "1110110111110001" "1100110100010010" "1010110100000001"
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Explorer
Explorer
499 Views
Registered: ‎03-17-2011

Re: vhdl program

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Can you update the waveform with data_count and data?

 

--Sebastien
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