I have created a test bench in order to run my simulation... basically I have a module and it only takes a clock as an input... how can I view the internal signals of that module?
module SCDP_tb();reg Clk;always begin Clk <= 0; #10; Clk <= 1; #10;endSCDP singlecycle(Clk);endmodule
Here's the module it self:
module SCDP(Clk);input Clk;wire Zero, Sign;wire RegWrite, MemRead, MemWrite, Beq, Bne, Bgtz, Blz, Bgez, Bltz, BranchMuxControl, BranchVal, Shift, HIWrite, LOWrite;wire [1:0] RegDst;wire [1:0] PCSrc;wire [1:0] ALUSrc;wire [1:0] MemtoReg;wire [3:0] Type;wire [4:0] ALUOp;wire[31:0] A4ALURes;wire[31:0] ReadData;wire[31:0] ReadData1;wire[31:0] ReadData2;wire[31:0] ALUSrc1;wire[31:0] ALUSrc2;wire[31:0] ALUResult;wire[31:0] pcinp;wire[31:0] pcout;wire[31:0] SignExtd;wire[31:0] ZeroExtd;wire[31:0] SLRes;wire[31:0] AddRes;wire[31:0] Instruction;wire[31:0] WriteData;wire[31:0] JumpOutput;wire[31:0] BranchMuxRes;................................................endmodule
Problem is, how can I view the signals inside SDCP? Such as Type, JumpOutput, etc..etc.. all I can see in my ISim is the Clk:
I can't see other signals besides the Clk, I want to see some other signals inside the module...
