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Explorer
Explorer
14,043 Views
Registered: ‎11-11-2013

vivado 2015.1 simulation error (Failure: ERROR:add_1 must be in range [-1,DEPTH-1])

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Hi there,

 

I tried to use vivado 2015.1 to run behavorial simulation for my own IP at the top level. 

The systhnsis and implementation succeeded. Then I ran the functional simualation with default simulation settings.

 

I also used the same test bench to run the simulation, but previously it worked. The difference is that I added FIR compiler IP here.

 

 

  FIR_Filter FIR_filter_decimator (
.aresetn(DAQ_resetn), // input wire aresetn
.aclk(sys_clk), // input wire aclk
//// Inbound slave AXIS stream
.s_axis_data_tvalid(s_axis_data_tvalid_dye_FIR), // input wire s_axis_data_tvalid
.s_axis_data_tready(s_axis_data_tready_dye_FIR), // output wire s_axis_data_tready
.s_axis_data_tlast(s_axis_data_tlast_dye_FIR), // input wire s_axis_data_tlast
.s_axis_data_tdata(s_axis_data_tdata_dye_FIR), // input wire [63 : 0] s_axis_data_tdata
//// Outbound master AXIS stream
.m_axis_data_tvalid(m_axis_data_tvalid_dye_FIR), // output wire m_axis_data_tvalid
.m_axis_data_tready(m_axis_data_tready_dye_FIR), // input wire m_axis_data_tready
.m_axis_data_tlast(m_axis_data_tlast_dye_FIR), // output wire m_axis_data_tlast
.m_axis_data_tdata(m_axis_data_tdata_dye_FIR) // output wire [63 : 0] m_axis_data_tdata
);

 

Hereby the error messages I got from the vivado Tcl console:

......

......

Failure: ERROR:add_1 must be in range [-1,DEPTH-1]
Time: 35 ns Iteration: 2
$finish called at time : 35 ns : File "***/Data8**_v1_0.v" Line 861
INFO: [USF-XSim-96] XSim completed. Design snapshot 'TB_data_mover_bridge_behav' loaded.
INFO: [USF-XSim-97] XSim simulation ran for 1000ns
launch_simulation: Time (s): cpu = 00:00:11 ; elapsed = 00:00:59 . Memory (MB): peak = 1808.762 ; gain = 4.176
run 10 us
Warning: NUMERIC_STD."=": metavalue detected, returning FALSE
Time: 35 ns Iteration: 2
Warning: NUMERIC_STD."=": metavalue detected, returning FALSE
Time: 35 ns Iteration: 2
Failure: ERROR:empty_1 and not_empty_1 are inconsistent
Time: 35 ns Iteration: 2
$finish called at time : 35 ns : File "***/Data8**_v1_0.v" Line 861

 

 

I checked line 861 in the source file, it seems ok. 

Any ideas?

thx

Sam

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1 Solution

Accepted Solutions
Moderator
Moderator
23,973 Views
Registered: ‎04-17-2011

Re: vivado 2015.1 simulation error (Failure: ERROR:add_1 must be in range [-1,DEPTH-1])

Jump to solution

This is issue with the testbench where in the process which drives the clk signal cause a clock event at 0 time which causes an issue with the counter add_1 in FIR IP. The solution is to rephrase the clock process in your testbench below:

 

always
begin
#(CLK_PERIOD/2) clk <= ~clk;
end

 

TO

 

always
begin
 clk = 1'b1;
 #(CLK_PERIOD/2) clk = 1'b0;
 #(CLK_PERIOD/2);
end

 

With this the error shouldnt happen.

Regards,
Debraj
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5 Replies
Xilinx Employee
Xilinx Employee
14,016 Views
Registered: ‎04-16-2012

Re: vivado 2015.1 simulation error (Failure: ERROR:add_1 must be in range [-1,DEPTH-1])

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Hello Sam,

 

Is it possible to share your testcase here to debug the issue?

 

Check how add_1 is declared in your code and its range?

 

Thanks,

Vinay

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Explorer
Explorer
13,995 Views
Registered: ‎11-11-2013

Re: vivado 2015.1 simulation error (Failure: ERROR:add_1 must be in range [-1,DEPTH-1])

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Hi Vinay,

There is  add_1 is declared in my project.

 

Hereby the FIR ip and test bench files FYI. 

I tested the ip with Vivado 2015.1 and win7 64bit. What I found is that the direct cause is the input of s_axis_data_tvalid to the FIR ip. If this pin is kept at low or high  all the time, there is no simulation errror.

 

Please take a look. thx.
Sam

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Moderator
Moderator
23,974 Views
Registered: ‎04-17-2011

Re: vivado 2015.1 simulation error (Failure: ERROR:add_1 must be in range [-1,DEPTH-1])

Jump to solution

This is issue with the testbench where in the process which drives the clk signal cause a clock event at 0 time which causes an issue with the counter add_1 in FIR IP. The solution is to rephrase the clock process in your testbench below:

 

always
begin
#(CLK_PERIOD/2) clk <= ~clk;
end

 

TO

 

always
begin
 clk = 1'b1;
 #(CLK_PERIOD/2) clk = 1'b0;
 #(CLK_PERIOD/2);
end

 

With this the error shouldnt happen.

Regards,
Debraj
----------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful and reply oriented.
----------------------------------------------------------------------------------------------
Visitor hutchid
Visitor
13,057 Views
Registered: ‎08-04-2010

Re: vivado 2015.1 simulation error (Failure: ERROR:add_1 must be in range [-1,DEPTH-1])

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I also had this error but the fix suggested by debrajr did not work.

 

s_axis_data_tvalid was not driven at startup in my design, once I changed this I was able to Simulate

 

Hopefully this helps somebody else

Highlighted
Observer prashanth453
Observer
1,296 Views
Registered: ‎03-16-2017

Re: vivado 2015.1 simulation error (Failure: ERROR:add_1 must be in range [-1,DEPTH-1])

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hi all,

I am got the same error while simulating the FIR compiler in vivado 16.2.before fir compiler i have dds and cic working fine but after adding the FIR Compiler only it shows the simulation was stoped.

Failure: ERROR:empty_1 and not_empty_1 are inconsistent
Time: 77500 ps Iteration: 1
$finish called at time : 77500 ps

 

please help me out in this regard

 

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