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dsula
Adventurer
Adventurer
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Registered: ‎01-14-2008

vivado simulator bug

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Please consider the code below.

The code sets signal a1 and a2 high with no further functionality.

Unfortunately this code does not simulate in viviado simulator. The simulator gets stuck at time 0 forever.

See screenshot at the end of the post.

I assume this is a bug in vivado simulator, as this code simulates without problem using modelsim.

Any comment is appreciated.

 

`timescale 1ns/1ps
module top();

logic a1;
logic a2;

x1 u1(.a1(a1), .a2(a2));
x2 u2(.a2(a2), .a1(a1));
endmodule

module x1(a1, a2);
input a1;
logic a1;
output a2;
logic a2;

logic tmp;

always_comb begin
   a2 = 0;
   a2 = 1;
   tmp = a1;
end
endmodule

module x2(a2, a1);
input a2;
logic a2;
output a1;
logic a1;

logic tmp;

always_comb begin
   a1 = 0;
   a1 = 1;
   tmp = a2;
end
endmodule

stuck_at_0ns.JPG

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amaccre
Moderator
Moderator
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Registered: ‎04-24-2013

Hi @dsula,

I have checked this in Vivado Simulator and can see the difference in behaviour when compared to Questa or Modelsim.

I will file a Change Request to ask that this is fixed in a future release of the tools.
I cannot guarantee that it will be fixed in the 2020.1 release as this ioutside my control but I will ask.

Best Regards
Aidan

 

 

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9 Replies
baring42read
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Adventurer
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Registered: ‎08-28-2019

There are few things I have noticed with your code.

1)  Instead of defining a1 and a2 twice( as input/output  and logic), you define as 

module x1(a1, a2);
input logic a1;
output logic a2;
module x2(a1, a2);
input logic a1;
output logic a2;

2) There is an internal signal temp  defined for both modules , a signal assigned to it but not used. This is certainly not causing your problem but the signal is unused.

3) At the level of the test, signals are used both as input and output for modules x1 and x2 respectively. So, I will suggest you do something like

logic a1;
logic a2_1;
logic a1_2;
x1 u1(.a1(a1), .a2(a2_1));
x2 u2(.a2(a2_1), .a1(a1_2));

 

 

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dsula
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Registered: ‎01-14-2008

Thank you for your reply.

Your points are well taken but the code is writtten such because it's a testcase showing the failure of the simulator. The code makes no sense beyond being a test case.

The coding style is actually automatically generated code by some cadence tool, which I reduced to an readable test case.

Changing the sub-modulde definitions from K&R style to ANSI for example makes the case work without problem.

There is an issue with the vivado simulator that it cannot simulate this code, yet with trivial modifications it simulates without problems.

 

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himalayan_fpga
Contributor
Contributor
829 Views
Registered: ‎10-25-2019

Here, the problem is not with the syntax or with vivado simulator but with logic itself. What you've done is created a zero delay loop oscillator. Here, x1 module takes input as a1 and gives output as a2 with zero delay. Now, this a2 is fed to x2 as input and it produces output a1 (again with zero delay). Now, for some reason, you've fed that output form x2 to input to x1. So, ideally you'd have infinite loop in just time zero and the simulation cannot move further. 
Now if you want simulation to run, either add some delay element or sensitivity list in always block or do not feedback the output form x2 to x1. 
Feel free to accept as solution if it answers your question.

Regards,
jagannath@logictronix.com
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dsula
Adventurer
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Registered: ‎01-14-2008

Thank you for your reply.

Unfortunately I cannot agree. There is no oscillation. And even if there were an oscillation the simulator would stop with a delta timestep error. But it doesn't. The simulator just hangs, indefinitly. Also simulation works fine with modelsim.

The code simply sets top level logic signal a1 and a2 to static high. The inputs into the module have no function at all.

I was able to simplify the code further, removing 1 module, showing the same simulation issue. See code below.

Also note, that simply changing the K&R module definition syntax to ANSI syntax will RESOLVE the issue. Simulation works.

'timescale 1ns/1ps
module top();​
​
logic a1;​
logic a2;​
​
x1 u1(.in(a1), .out(a2));​
x1 u2(.in(a2), .out(a1));​
endmodule​
​
module x1(in, out);​
input in;​
logic in;​
output out;​
logic out;​

// REWRITING THE MODULE HEADER LIKE THIS WILL RESOLVE THE SIMULATION ISSUE
// module x1(input logic in, output logic out); ​ logic tmp;​ ​ always_comb begin​ out = 0;​ out = 1;​ tmp = in;​ end​ endmodule​
amaccre
Moderator
Moderator
773 Views
Registered: ‎04-24-2013

Hi @dsula,

I have checked this in Vivado Simulator and can see the difference in behaviour when compared to Questa or Modelsim.

I will file a Change Request to ask that this is fixed in a future release of the tools.
I cannot guarantee that it will be fixed in the 2020.1 release as this ioutside my control but I will ask.

Best Regards
Aidan

 

 

------------------------------------------------------------------------------------------------------------------
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Give Kudos to a post which you think is helpful and may help other users
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amaccre
Moderator
Moderator
688 Views
Registered: ‎04-24-2013

HI @dsula ,

I received a reply from the factory that XSim's behaviour is correct, as the logic of code itself written such a way creating this hang.

The testcase is stuck at 0fs in XSim as an infinite loop. The reason for this is the 2 instances u1 and u2 in module "top".
Here, x1 module using instance u1 takes input as a1 and gives output as a2 with zero delay.

Now, this a2 is fed to instance u2 as input and it produces output a1 with zero delay.

This creates the zero delay loop and triggers the always block continously, which causes simulator to hang.

As the behaviour is correct with regard to the Language Reference Manual it won't be changed.

Best Regards
Aidan

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dsula
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Registered: ‎01-14-2008

Hi@amaccre 

Thank you for your reply. Unfortunately I cannot agree. For the following reasons:

1. the code synthesizes in both vivado and synopsys DC without any problems. If there were a 0-delay oscillation, the synthesizers would complain.

2. the code simulates without issue in Modelsim. Only vivado sim can't handle it.

3. Simply changing the module definition style from K&R (old school) to ANSI (new school) without any further change in code will make it work properly in vivado sim. See comment in the code below for what I mean.

 

@amaccre wrote:

The testcase is stuck at 0fs in XSim as an infinite loop. The reason for this is the 2 instances u1 and u2 in module "top".
Here, x1 module using instance u1 takes input as a1 and gives output as a2 with zero delay.

Now, this a2 is fed to instance u2 as input and it produces output a1 with zero delay.

The output (pin 'out') of module x1 is not dependent on pin 'in'. The output 'out' is constant '1' and never changes. It should NOT retrigger an evaluation because the inputs of u1 and u2 never change. Nothing in this code moves. Both signals 'a1' and 'a2' are fixed to 1. There is no oscillation.

 

'timescale 1ns/1ps
module top();​
​
logic a1;​
logic a2;​
​
x1 u1(.in(a1), .out(a2));​
x1 u2(.in(a2), .out(a1));​
endmodule​
​
module x1(in, out);​
input in;​
logic in;​
output out;​
logic out;​

// PLEASE EXPLAIN WHY REWRITING THE MODULE DEFINITION LIKE
// THIS WILL RESOLVE THE SIMULATION ISSUE: // --------> module x1(input logic in, output logic out); ​ logic tmp;​ ​ always_comb begin​ out = 0;​ out = 1;​ tmp = in;​ end​ endmodule​

 

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amaccre
Moderator
Moderator
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Registered: ‎04-24-2013

Hi @dsula ,

The code was analysed by the factory and the infinite loop is explained in the following stages.

1) U1 get instatiated and trigger always_comb block, which will change a2 value from x->0 as a2 is output of U1

2) U2 get instantiated and trigger always_comb block which in first line of code out=1 , which triggers U1 again as out of U2 is connected with input of U1

3) U1 always block get triggered and which  make again first line out =1 , which will trigger U2 again as out of U1 is connected with input of U2 block.

4) So , we are creating deadlock situation here which will continuously make point 2 and point 3 repeat infinitely .

Hence Xsim is behaving correctly as explained above.

Best Regards
Aidan

 

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dsula
Adventurer
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Registered: ‎01-14-2008

@amaccre 

Ok.

But why does changing this few lines (K&R declaration style)

 

module x1(in, out);
input in;
logic in;
output out;
logic out;

to this single line (ANSI style) make it work?

 

module x1(input logic in, output logic out);

make it work?

 

 

And why does the synthesizer create the expected logic, namely constant 1 output on a1 and a2?  It builds the expected logic, no oscillator, no complaint about loops.

Capture.PNG

 

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