Iam use ISE11.4 and Modelsim 6.5. and my major work is write ip core use VHDL .
We know that there are Behavior Simulation ,Post Translate Simulation, Post Map Simulation and Post Route Simulation in modelsim.
In my former designs (code line less than 5000), I just do Behavior Simulations , and the result is correct after imported as peripheral ip core in edk design.
But this time ,after fininshed my ip design with VHDL, I creat and import it to peripheral, I find that My ip output in edk (as a peripheral) is different from the behavior simulation output in modelsim 。and more, some of the result data is changed time to time with my download times。
SO,i back to post simulation , run Post Translate Simulation, Post Map Simulation and Post Route Simulation in modelsim, But the simulated-result of these simulation model is different from one to one. so ,there are five different results as follows:
1) behavior simulation results.
2) Post Translate Simulation results.
3) Post Map Simulation results
4) Post Route Simulation results.
5) edk verify results after imported as peripheral.
I'd like to know why these results are different ? how to check the mistake or how to resolve this problem?
I also checked the time constraints, but there are no change to result.
Any information is helpful, or any reference docs is needed.
Thanks ,Sincerely!
