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Visitor aae65
Visitor
3,087 Views
Registered: ‎06-17-2013

wrong results using ISIM

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Hello,

I am simulating a vhdl module and i am getting illogical results in the ISIM. I attached three photos in which i am using the step function to track the parts of the code that are being used. When i set the flag to 1, the statement under the case when the flag is 0 is visited after it (and vice versa). These statement are all inside a process and should be executed sequentially, and i am not sure of the cause behind this bahavior. Any thoughts?

Thank You

Capture.JPG
Capture2.JPG
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Teacher eilert
Teacher
3,900 Views
Registered: ‎08-14-2007

Re: wrong results using ISIM

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Hi,

seems like you are not aware of the difference between signals and variables in VHDL.

 

Signal drivers are updated at the end of a process or the next wait statement.

Until then,reading from a signal always gives the value it had when entering the process.

 

Only variables are updated immediately inside aprocess.

 

  a <= b;

  a <= a+a;

 

results in 2*a inside a process.

 

  a := b;

  a := a+a;

 

results in 2*b, notice the difference.

 

Have a nice simulation

  Eilert

 

 

 

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Teacher eilert
Teacher
3,901 Views
Registered: ‎08-14-2007

Re: wrong results using ISIM

Jump to solution

Hi,

seems like you are not aware of the difference between signals and variables in VHDL.

 

Signal drivers are updated at the end of a process or the next wait statement.

Until then,reading from a signal always gives the value it had when entering the process.

 

Only variables are updated immediately inside aprocess.

 

  a <= b;

  a <= a+a;

 

results in 2*a inside a process.

 

  a := b;

  a := a+a;

 

results in 2*b, notice the difference.

 

Have a nice simulation

  Eilert

 

 

 

View solution in original post

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Visitor aae65
Visitor
3,076 Views
Registered: ‎06-17-2013

Re: wrong results using ISIM

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Thank you very much!

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