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1,386 Views
Registered: ‎05-23-2018

xcelium errors in xilinx IP

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I have a project in Vivado 2018.1 running on Linux and I am trying to simulate using xcelium. I followed instructions for 3rd party simulators to compile simulation libraries for the xcelium, but I get elaboration errors from the Xilinx IP in my project. For example:

 

xmelab: *E,CFIRWM (/project/fpga/rtl/ip/clk_wiz_0/clk_wiz_0_sim_netlist.v,95|23): The value being mapped from Verilog parameter to VHDL generic BUFGCTRL:PRESELECT_I0 (/tools/Xilinx/Vivado/Vivado/2018.1/data/vhdl/src/unisims/primitive/BUFGCTRL.vhd: line 48, position 17) does not lie within the range of the type of generic.
Foreign entity/architecture elaboration: clk_pll@clk_wiz_0<module>.inst@clk_wiz_0_clk_wiz_0_clk_wiz<module>.clkout1_buf
.PRESELECT_I1("FALSE"))
|

 

xmelab: *E,CFITWM (/project/fpga/rtl/ip/clk_wiz_0/clk_wiz_0_sim_netlist.v,96|24): Type or width mismatch between Verilog parameter override and VHDL generic BUFGCTRL.PRESELECT_I1 (/tools/Xilinx/Vivado/Vivado/2018.1/data/vhdl/src/unisims/primitive/BUFGCTRL.vhd: line 49, position 17).
Foreign entity/architecture elaboration: clk_pll@clk_wiz_0<module>.inst@clk_wiz_0_clk_wiz_0_clk_wiz<module>.clkout1_buf
.CLKFBOUT_USE_FINE_PS("FALSE"),
|

 

xmelab: *W,CUNOTB: component instance is not fully bound (jesd204_0_i@jesd204_0<module>.inst@jesd204_0_jesd204_0_support<module>.i_jesd204_phy@jesd204_0_jesd204_0_phy<module>.inst@jesd204_0_jesd204_0_phy_support<module>.jesd204_phy_block_i@jesd204_0_jesd204_0_phy_block<module>.jesd204_0_phy_gt@jesd204_0_jesd204_0_phy_gt<module>.inst@jesd204_0_jesd204_0_phy_gt_init<module>.jesd204_0_phy_gt_i@jesd204_0_jesd204_0_phy_gt_multi_gt<module>.gt0_jesd204_0_phy_gt_i@jesd204_0_jesd204_0_phy_gt_GT<module>.gtxe2_i@GTXE2_CHANNEL(GTXE2_CHANNEL_V):GTXE2_CHANNEL_INST) [File:GTXE2_CHANNEL.vhd, Line:2219].


xmelab: *W,CUNOTB: component instance is not fully bound (jesd204_0_i@jesd204_0<module>.inst@jesd204_0_jesd204_0_support<module>.i_jesd204_phy@jesd204_0_jesd204_0_phy<module>.inst@jesd204_0_jesd204_0_phy_support<module>.jesd204_phy_gt_common_i@jesd204_0_jesd204_0_phy_gt_common_wrapper<module>.jesd204_0_common@jesd204_0_jesd204_0_phy_gtwizard_0_common<module>.gtxe2_common_i@GTXE2_COMMON(GTXE2_COMMON_V):GTXE2_COMMON_INST) [File:GTXE2_COMMON.vhd, Line:407].
.CLKCM_CFG("TRUE"),
|

 

xmelab: *E,CFIRWM (/project/fpga/rtl/ip/jesd204_0/jesd204_0_sim_netlist.v,4161|20): The value being mapped from Verilog parameter to VHDL generic IBUFDS_GTE2:CLKCM_CFG (/tools/Xilinx/Vivado/Vivado/2018.1/data/vhdl/src/unisims/primitive/IBUFDS_GTE2.vhd: line 36, position 14) does not lie within the range of the type of generic.
Foreign entity/architecture elaboration: jesd204_0_i@jesd204_0<module>.inst@jesd204_0_jesd204_0_support<module>.i_shared_clocks@jesd204_0_jesd204_0_clocking<module>.ibufds_refclk0
.CLKRCV_TRST("TRUE"),
|

 

There are a total of 16 errors from these two IPs all of the types shown above.

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1,307 Views
Registered: ‎05-23-2018

I am not able up upgrade the simulator at this time. However I did somehow solve the problem by deleting all of the compiled simulation libraries and regenerating them. 

View solution in original post

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Moderator
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Registered: ‎04-24-2013

Hi @daniel.brunina,

 

Which version of the Vivado tools are you using and which version of Xcelium?

 

Also when you compiled the simulation libraries, did you get any errors?

 

Thanks
Aidan

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Registered: ‎05-23-2018

Hi Aidan, thanks for the reply. My Vivado version is 2018.1. Xcelium is version 16.11.

 

There are no errors in my compile_simlib. I compiled only unisim, not simprim. And I left the four checkboxes unchecked (compile xilinx IP, overwrite the current pre-compiled libraries, compile 32-bit libraries, and verbose). I am using a Kintex-7 so I set family to only Kintex-7.

 

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Moderator
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Registered: ‎03-16-2017

Hi @daniel.brunina,

 

Please upgrade the xcelium simulator version to 17.10.005 since it is the supported version with Vivado 2018.1 and then check. 

 

xcel.JPG

 

Regards,

hemangd

 

Regards,
hemangd

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Highlighted
1,308 Views
Registered: ‎05-23-2018

I am not able up upgrade the simulator at this time. However I did somehow solve the problem by deleting all of the compiled simulation libraries and regenerating them. 

View solution in original post

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