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jjohnny
Visitor
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Registered: ‎03-29-2019

xsim error when using arrays [Vivado 2018.2 possible bug report]

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Hi,

I observe an error when using Vivado 2018.2 simulation.

If in a construct like "result1 = array01[pointer].data01[1:0];" the pointer changes, the output does not change. However it does change if I assign the array01[pointer] first.

System Verilog example on Vivado 2018.2

module tb01(  );

    struct packed {
        logic [31:0] data01;
        logic [31:0] data02;
    }  array01 [1:0], currentArray;
    
    logic [0:0] pointer;
    logic [31:0] result1;
    logic [31:0] result2;

    initial begin
    	pointer = 0;
    	array01[0].data01 = 32'h12;
        array01[0].data02 = 32'h13;
        array01[1].data01 = 32'h23;
        array01[1].data02 = 32'h24;
    	#100
        pointer = 1;
        #100
        pointer = 0;
        #100
        pointer = 1;
    end

    //result2 shows incorrect values but should be identical to result2
    assign result1 = array01[pointer].data01[1:0];

    assign currentArray = array01[pointer];
    //result2 shows the correct values
    assign result2 = currentArray.data01[1:0];

endmodule

result2 shows the correct result but result1 does always show the result of array01[0].

Regards,

Johannes

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graces
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480 Views
Registered: ‎07-16-2008

I gave it a try in 2018.3 and the issue looks to have been fixed.

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graces
Moderator
Moderator
481 Views
Registered: ‎07-16-2008

I gave it a try in 2018.3 and the issue looks to have been fixed.

-----------------------------------------------------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
If starting with Versal take a look at our Versal Design Process Hub and our Versal Blogs.
-----------------------------------------------------------------------------------------------------------------------

View solution in original post

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