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Explorer
Explorer
7,943 Views
Registered: ‎07-28-2010

1 PPS TO FPGA

Hi

 

I am trying to connect 1PPS from GPS receiver to one of FPGA   I/O pins. I wish the FPGA to perform some tasks  once it sees the rising edge of 1pps in the I/O pin. I am using verilog for hdl.  I did not get a point to impelement this in the code.  I am not sure what will be the status of I/O pins when it sees the rising edge ?

 

Any help would be appreciated

 

 

Regards

 

Faisal

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6 Replies
Instructor
Instructor
7,938 Views
Registered: ‎07-21-2009

Re: 1 PPS TO FPGA

input  InPulse;

 

reg InPulseQ;

reg InPulseQQ;

 

wire RisingEdgeDetected;

 

always @ ( posedge Clock)

  begin

    InPulseQ  <= InPulse;   // register for input synchronization

    InPulseQQ  <=  InPulseQ;  // one clock cycle delay

  end

 

assign RisingEdgeDetected = InPulseQ && ~InPulseQQ;  // single cycle pulse when rising edge detected

 

// NOTE:  Clock freq must be high enough to capture InPulse;

// in UCF or Planahead, specify pin number (and IO standard) for InPulse input pin

 

 

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
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Explorer
Explorer
7,907 Views
Registered: ‎07-28-2010

Re: 1 PPS TO FPGA

Many Thanks

 

DCM clock and 1 pps are not synchronised. In that case in the always block  code

 

InPulseQ  <= InPulse ,

 

InPulse is not necessary be the rising edge of 1 pps .

 

Also I can't follow one clock cycle time delay in the code

 

 

I am here with explaining the problem more detail

 

FPGA has free running counter which is triggered with rising edge clock of 100 MHz clock from DCM. When the counter reaches a certain value ,  I/O pin in which 1 pps is connected is opened and will wait for the rising edge of  1 pps. Counter value is recorded in buffer once rising edge of 1 pps pulse is detected in th I/O pin.

 

 

Thanks and Regards

 

Faisal

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Instructor
Instructor
7,900 Views
Registered: ‎07-21-2009

Re: 1 PPS TO FPGA

It sounds like you know what you need to do.  What help are you asking?

 

Your next step is to write your code and run it on a simulator.  WebISE has all the tools you need..

 

- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
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Explorer
Explorer
7,860 Views
Registered: ‎07-28-2010

Re: 1 PPS TO FPGA

Thanks BOB

 

I have written HDL code as follows.

 

Apart from the DCM clock , I have used an always block with senstivity  list as pps clock as

 

always @ (posedge PPSCLK)

 

This 1 pps is directly connected to I/O pin of FPGA

 

Simulation works fine.  My question here is can we   CLOCK  the FPGA other than from DCM ?

 

Thanks

 

Faisal

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Instructor
Instructor
7,858 Views
Registered: ‎07-21-2009

Re: 1 PPS TO FPGA

You can select just about any signal or IO pin you want as your clock source.  Have you tried this?

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
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Historian
Historian
7,844 Views
Registered: ‎02-25-2008

Re: 1 PPS TO FPGA

 


@pfaisalbe wrote:

Thanks BOB

 

 

Simulation works fine.  My question here is can we   CLOCK  the FPGA other than from DCM ?

 

Thanks

 

Faisal


FPGA registers can be clocked by any signal you wish to use.  The clock doesn't have to be from a DCM.

 

----------------------------Yes, I do this for a living.
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