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Visitor dlachance_00
Visitor
9,112 Views
Registered: ‎09-05-2007

200AN (4C-ES) TAP Controller problems?

  Has anyone else had trouble with these 200AN parts?  I have 10 PCBs with these devices on the same JTAG chain as an ARM7 CPU.  The software guys can access the ARM7 with thier JTAG debug tools, but I can't seem to access the FPGA.  Since they can send and receive data just fine, I assume that the chain is wired correctly.  Also, iMPACT correctly identifies the FPGA when I auto-initialize the chain, another good sign.  But, then I can't read the IDCODE, so I can't do anything else with the FPGA.
  I've gone so far as to use a third-party JTAG programmer and put a scope on the 4 JTAG lines to see what's going on.  I can see that when the TAP controller is RESET, then the DR is loaded with the IDCODE, so all I need to do is clock 32 cycles through the DR to get the ID (similar to what iMPACT must do to initialize the chain).  This works great, so the TCK, and TDO must be correct.  I also think TMS must be correct if I can change the TAP controller state to RESET, then to Shift DR, and back to IDLE.  But, as soon as I send the IDCODE instruction (0x09) to the IR, all I can get out of the DR is 0xFFFFFFFE.  Any idea what might cause this?
  I openned a webcase yesturday, but I thought I'd try this approach as well...  Without this JTAG port working, I can't get any farther until the software guys are ready to program the FPGA via Slave Parallel.  This could be weeks of lost FPGA-Hardware integration time...
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2 Replies
Explorer
Explorer
9,109 Views
Registered: ‎08-13-2007

Re: 200AN (4C-ES) TAP Controller problems?

if you have 2 devices in chain then
 
TLR
DR-SHIFT
should shift out 32 + 32 bit IDCODES
well the ARM JTAG is not fully compliant JTAG but it will still spit out a kinda IDCODE
 
when you send anything to IR you must use proper header-trailed padding or the FPGA will not see the command properly
 
but i guess you did set the IR length manually in impact already
 
if you have atmel ARM7 try changing to the other JTAG TAP chain,
 
an ARM (at least SAM7) is generically not a good idea to have in FPGA JTAG chain :(, I had lots of problems with it some while ago. It's ok and it will also work, but.. some hassle can be expected.
 
eh, but getting the FPGA programmed via slave parallel is just a few hours of work max, so hit the software guys !
 
Antti Lukats
 
 
 
 
 
 
 
 
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Xilinx Employee
Xilinx Employee
9,091 Views
Registered: ‎08-28-2007

Re: 200AN (4C-ES) TAP Controller problems?

This sounds alot like a problem on the TDI line. The auto initialise chain does not use the TDI of the first device. The “Initialize Chain” operation will place each device in the TLR state and then the Shift-DR TAP state. At this point, the IDCODEs from each device will be shifted out of the devices and into the TDO pin on the header. If this operation succeeds, the TDI to TDO connections between the device, TMS, TCK, and TDO from the last device to the header are proven to be intact. The only line that has not been tested is the connection from the TDI pin of the header to the first device. If initialise chain works and get devcie ID doesn't its a good chance there is a problem betwenn the header and TDI of the first device.

-P

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