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Observer stmilch
Observer
3,799 Views
Registered: ‎04-16-2010

3 state busses on IO

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I want to use the 3-state flip-flops in the IOBs together with busses. These flip-flops are equivalent and the copies are removed even using KEEP on the 3-state enable bus.

 

process (Clk, Reset)
begin
    if (Reset = '1') then
        DisableOut <= (others => '1');
        DataOut <= (others => '0');
    elsif (Clk'event and Clk='0') then
        if (DriveBus = '1') then
            DisableOut <= (others => '0');
        else
            DisableOut <= (others => '1');
        end if;

        DataOut <= DataToOutput;
    end if;
end process;

 

All busses are std_logic_vector(31 downto 0); Packing into IOBs is enabled.

 

What is the proper constraint to have one 3-state-flip flop implemented for every data bit?

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Accepted Solutions
Scholar drjohnsmith
Scholar
4,762 Views
Registered: ‎07-09-2009

Re: 3 state busses on IO

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Hi

 

two trains of thought on this.

 

1) Infer everything, and if your constraints are correct in the UCF, timing etc, then the design will work no matter what the compiler does.

 

2) instantiate everything, no constraints, and let you decide placment,

 

between the tto is what most people do.

 

Do you have the timing constraints set up in the ucf ?

 Have a look here at austins blog

http://forums.xilinx.com/t5/PLD-Blog/Timing-Constraints-Part-4-of-5/ba-p/66696

 

 If you want to instantiate, look here

http://www.xilinx.com/itp/xilinx9/books/docs/s3edl/s3edl.pdf

 

 and here

http://www.xilinx.com/support/documentation/user_guides/ug331.pdf

 

 

 Oh and be aware how things change in different versions of ISE.

 

 

Basicaly, if you want to exactly place the lib blocks, then you can, 

 if you want to infer and use the timing constrainst, then you can.

 

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3 Replies
Scholar drjohnsmith
Scholar
3,786 Views
Registered: ‎07-09-2009

Re: 3 state busses on IO

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Hi

 

whats the device ?

 

Easiest way to force the things into where you want, but not the most elegant, is generaly to instantiate not infer.

 

 

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Observer stmilch
Observer
3,779 Views
Registered: ‎04-16-2010

Re: 3 state busses on IO

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The device is a Spartan3E.

 

I would instanciate a output FF with output 2 state FF if there would be any in the language templates.

 

But sincerely there must be a way to tell ISE how to do generate 3-state bus drivers with 3-state flipflops in the IOBs.

0 Kudos
Scholar drjohnsmith
Scholar
4,763 Views
Registered: ‎07-09-2009

Re: 3 state busses on IO

Jump to solution

Hi

 

two trains of thought on this.

 

1) Infer everything, and if your constraints are correct in the UCF, timing etc, then the design will work no matter what the compiler does.

 

2) instantiate everything, no constraints, and let you decide placment,

 

between the tto is what most people do.

 

Do you have the timing constraints set up in the ucf ?

 Have a look here at austins blog

http://forums.xilinx.com/t5/PLD-Blog/Timing-Constraints-Part-4-of-5/ba-p/66696

 

 If you want to instantiate, look here

http://www.xilinx.com/itp/xilinx9/books/docs/s3edl/s3edl.pdf

 

 and here

http://www.xilinx.com/support/documentation/user_guides/ug331.pdf

 

 

 Oh and be aware how things change in different versions of ISE.

 

 

Basicaly, if you want to exactly place the lib blocks, then you can, 

 if you want to infer and use the timing constrainst, then you can.

 

0 Kudos