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Registered: ‎03-23-2014

ADC Data Collection in Spartan 6 (90% resource utilized)



I'm using a Spartan 6 LX 150 in which i'm interfacing a transceiver IC. I need to send data in Double data rate both - while tranmitting to DAC and receiving from ADC.


Apart from this, there are other algorithms that are inside the FPGA, which have consumed 98% DSP Slices and majority of the LUTs and Slices. The FPGA PAR giving a very high timing failures. Besides, with all these designs, the transmitting data to DAC and receiving data from ADC is also getting spoilt.


The FPGA routing results in poor setup and hold times, resulting in this problem.


I've tried giving in OFFSET IN and OFFSET OUT constraints for the Data bus of ADC and DAC. Also have given the period for all the clocks used in the design.


Have also registered the ADC and DAC Data bus by multiple stages which is not helping too. Have tried creating pblocks for step by step smaller segments and still i've a huge timing failure.


Can somebody help me by telling how to properly send data and receive from Transceivers, with other logics inside the FPGA not affecting this segment of the design??



1. ADC Clock and DAC Clock:  30 MHz

2. Double Data Rate transmit and receive




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3 Replies
Registered: ‎07-21-2009

I'm using a Spartan 6 LX 150 in which i'm interfacing a transceiver IC

Can somebody help me by telling how to properly send data and receive from Transceivers?


Which transceiver?


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Community Manager
Registered: ‎07-23-2012

Hi Sharan,

With a very high utilization, you may need extra effort- drawing pblocks/ manual placement etc to meet timing.

You can refer to Timing Failure Design Scenarios section of for guidance on meeting the timing.

If possible, share the utilization report (.mrp) and timing report (.twr).

Please mark the post as "Accept as solution" if the information provided answers your query/resolves your issue.

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Registered: ‎03-23-2014

Hi Bob,


The Transceiver used is AD9361 from Analog Devices




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